E-viri
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Tae-Young Oh; Young-Soo Sohn; Seung-Jun Bae; Min-Sang Park; Ji-Hoon Lim; Yong-Ki Cho; Dae-Hyun Kim; Dong-Min Kim; Hye-Ran Kim; Hyun-Joong Kim; Jin-Hyun Kim; Jin-Kook Kim; Young-Sik Kim; Byeong-Cheol Kim; Sang-Hyup Kwak; Jae-Hyung Lee; Jae-Young Lee; Chang-Ho Shin; Yun-Seok Yang; Beom-Sig Cho; Sam-Young Bang; Hyang-Ja Yang; Young-Ryeol Choi; Gil-Shin Moon; Cheol-Goo Park; Seok-Won Hwang; Jeong-Don Lim; Kwang-Il Park; Joo Sun Choi; Young-Hyun Jun
2010 IEEE International Solid-State Circuits Conference - (ISSCC), 2010-Feb.Conference Proceeding
7 Gb/s/pin operation without bank group restriction in a GDDR5 SDRAM is achieved by skewed control logic and current-mode I/O sense amplifiers with regular calibration from replica impedance monitors. The bank-to-bank active time is shortened to 2.5 ns by a FIFO-based BLSA enabler, 2.0 ns latency V PP generator and active jitter canceler. The chip is fabricated in a 50 nm DRAM process in a 61.6 mm 2 die area.
