E-viri
-
Chih-Ping Chen; Hang-Ting Lue; Kuo-Pin Chang; Yi-Hsuan Hsiao; Chih-Chang Hsieh; Shih-Hung Chen; Yen-Hao Shih; Kuang-Yeu Hsieh; Tahone Yang; Kuang-Chao Chen; Chih-Yuan Lu
2012 Symposium on VLSI Technology (VLSIT), 06/2012Conference Proceeding
Despite vertical stacking, the lateral scaling of 3D NAND Flash is critically important because otherwise >;16 stacking layers are needed to be cost competitive to 20nm 2D NAND. In this work, we propose a 3D vertical gate (VG) NAND using a self-aligned independently controlled double gate (IDG) string select transistor (SSL) decoding method. The IDG SSL provides excellent program inhibit and read selection without any penalty of cell size increase, making our 3D VG NAND cell as scalable as conventional 2D NAND. We present the world's first <; 50nm (37.5nm) half-pitch 3D NAND. The BL decoding and page operation methods are illustrated in detail. This highly pitch scalable VG with IDG SSL approach provides a very cost competitive 3D NAND.
