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Zusing Yang; Fang-Hao Hsu; Lo Yueh Lin; Hong-Ji Lee; Nan-Tzu Lian; Tahone Yang; Kuang-Chao Chen; Chih-Yuan Lu
ASMC 2013 SEMI Advanced Semiconductor Manufacturing Conference, 05/2013Conference Proceeding
This paper describes a simple and systematic etching approach for the preparation of smooth vertical bit line (BL), stacked with multiple layers of SiO 2 (OX) and poly-Si (PL) films for the use in three-dimensional vertical gate (3DVG) NAND flash application. A successful shape evolution from tapered to acceptable BL profile with sub-10 nm critical dimension (CD) difference between bottom and top PL layers is performed by a recipe consisting of etch-trim-etch processing steps. This novel etch sequence is more advantageous than that of traditional simultaneous etch-deposition process for controlling profile shape of the multi-layer stack in the 3D NAND flash manufacturing.
