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Falchieri, D; Bruni, G; Bruschi, M; D'Antone, I; Dopke, J; Flick, T; Gabrielli, A; Grosse-Knetter, J; Joseph, J; Krieger, N; Kugel, A; Morettini, P; Polini, A; Rizzi, M; Schroer, N; Travaglini, R; Zannoli, S; Zoccoli, A
IEEE Nuclear Science Symposuim & Medical Imaging Conference, 2010-Oct.Conference Proceeding
An additional inner layer for the existing ATLAS Pixel Detector, called Insertable B-Layer (IBL), is under design and it will be installed by Phase I. New front-end readout ASICs fabrication (FE-I4) will replace the previous chips in this layer. The new system features higher readout speed - 160Mb/s per ASIC - and simplified control. The current data acquisition chains are composed of front-end and readout chips, Back-Of-Crate (BOCs) cards and ReadOut Driver cards (RODs). This paper presents a proposal for the new ROD board, which implements modern FPGAs and high-speed links with the detector and with the ATLAS TDAQ system.
