Testing plays an important role in controlling and ensuring required quality and reliability of manufactured integrated circuits (ICs) before supplying them to final users. Several types of testing are performed at different stages of the IC manufacturing process. One of them is the so-called burn-in testing (i.e., accelerated testing performed under elevated temperature and other stress conditions). Burn-in aims to accelerate detection and screening out of so-called "infant mortalities" (early-life latent failures). Burn-in is normally associated with lengthy test time and high cost, making it a bottleneck of the entire IC manufacturing process. It is no surprise, therefore, that much attention and effort has dedicated toward possible ways of reducing or even eliminating burn-in testing in IC manufacturing (for at least some types of products). This paper presents a methodology for burn-in test time reduction based on the use of the high-voltage stress test technique. Weibull statistical analysis is employed to model the infant-mortality-failure distribution. Weibull distribution parameters were estimated using the linear rectification method. The implemented industrial experimental study showed that burn-in duration can be significantly reduced with the application of the proposed approach