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Dai Zhang; Alvandpour, Atila
IEEE transactions on circuits and systems. II, Express briefs, 03/2016, Letnik: 63, Številka: 3Journal Article
This brief describes a 14-b 10-kS/s successive approximation register analog-to-digital converter (ADC) for biomedical applications. In order to achieve enhanced linearity, a uniform-geometry nonbinary-weighted capacitive digital-to-analog converter is implemented. In addition, a secondary-bit approach to dynamically shift decision levels for error correction is employed. To reduce the power consumption, the ADC also features a power-optimized comparator with bias control. Prototyped in a 65-nm CMOS process, the ADC consumes 1.98 μW and provides an effective number of bit (ENOB) of 12.5 bat 0.8 V while occupying an active area of 0.28 mm 2 .
