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Chang, Kai-Ping; Lien, Po-Chun; Yen, Chao-Chun; Chen, Po-Wei; Horng, Ray-Hua; Wuu, Dong-Sing
IEEE photonics technology letters, 12/2021, Letnik: 33, Številka: 24Journal Article
The fabrication process and light extraction efficiency of AlGaInP-based flip-chip micro- light-emitting diode (<inline-formula> <tex-math notation="LaTeX">\mu </tex-math></inline-formula>-LED) array chips are improved by employing a wafer-bonding process, patterned metal contact, and sidewall passivation layers. The epilayers with indium tin oxide (ITO) can be successfully transferred from the GaAs substrate to the sapphire substrate and bound. Three types of patterned n-metal are employed in the <inline-formula> <tex-math notation="LaTeX">\mu </tex-math></inline-formula>-LED as a self-aligning mask and light reflection layer, where the n-GaAs layer can be partially removed by the wet etching process. The dry etching process of MESA has been optimized by applying the BCl 3 gas in the inductively coupled plasma (ICP) system, which can suppress the etching rate of the sidewall and improve the etching depth uniformity. Consequently, the leakage current of the <inline-formula> <tex-math notation="LaTeX">\mu </tex-math></inline-formula>-LED array chip is decreased from 85 to 7 nA under the bias of −5 V. Moreover, three configurations of the metal contact/n-GaAs structures with Omnidirectional reflector (ODR) have been designed to reduce the emission light absorption, passivating the sidewall of MESA, and enhance the output power. Finally, the 0.52-in red <inline-formula> <tex-math notation="LaTeX">\mu </tex-math></inline-formula>-LED array with a chip size of <inline-formula> <tex-math notation="LaTeX">100\,\,\mu \text{m}\,\,\times 100\,\,\mu \text{m} </tex-math></inline-formula> and resolution of 138 pixels/in is realized when bonded with the drive IC. Consequently, the <inline-formula> <tex-math notation="LaTeX">\mu </tex-math></inline-formula>-LED array chips with ODR and patterned contact show the highest external quantum efficiency of 51.1% and relative output power enhancement of 441% compared to the chip with SiO 2 passivation layer and nonpatterned n-metal contact.
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