A three-dimensional (3D) integrated packaging method is proposed in this letter. Re-distributed layers (RDLs) are realized by integrating flexible printed circuit (FPC) boards onto gallium nitride (GaN) high electron mobility transistor (HEMT) dies to enlarge the electrodes area and the clearance between them. GaN HEMTs with RDLs are sandwiched between a multi-layer printed circuit board (PCB) and an active metal brazing (AMB) board. Additionally, components like decoupling capacitors, gate driver, digital isolator and isolated power supply are integrated into this package. Silver sintering processes are employed to maintain consistent processing temperature for multiple interconnections, addressing reliability concerns associated with conventional multi-temperature gradient soldering methods. Furthermore, sintered silver significantly improves both electrical and thermal performances. Power and thermal managements are decoupled by using a PCB and AMB substrate, resulting in low parasitic inductances, minimal thermal resistance and electric field shielding. The experiment-measured power loop inductance is as low as 0.54 nH, and the simulated thermal resistance from GaN die to AMB board bottom is only 0.05 ℃/W. A detailed description of manufacturing processes, thermal performance test, dynamic switching performance with circuit-level simulated verification are provided in this letter.