•The mechanism of negative bias instability in commercial silicon carbide Metal-Oxide-Semiconductor Field-Effect Transistors has been explained through the analysis of transient gate currents.•Experimental results demonstrate that near-interface traps with energy levels aligned to the valence band trap holes from the valence band by tunneling.•The transients in the gate current correspond to the trapping of holes by the near-interface traps.•The study demonstrates the impact of the aluminum implantation process on the p-type region, highlighting its role in hole trapping. This article explains the mechanisms of negative bias instability in commercial n-channel SiC metal–oxide semiconductor field-effect transistors (MOSFETs) by analysis of transient gate currents. The current–voltage measurements were performed at different temperatures along with capacitance–voltage measurements to characterise hole trapping and de-trapping in planar SiC MOSFETs. The experimental results reveal that near-interface traps (NITs) with energy levels aligned to the valence band trap holes from the valence band by tunneling, which is different from published results about NITs with energy levels aligned to the energy gap. The impact of the aluminium implantation process of the p-type region on hole trapping is also demonstrated. The presented analysis also reveals that the hole trapping by NITs is limited to the p-type region, indicating that the aluminium implantation process is responsible for the detected NITs.