碩士 國立交通大學 電子研究所 81 In this thesis, efficient pipelined, high throughput rate architectures for CORDIC algorithm are presented. Since the CORDIC operation is dependent on the sign of remaining rotation or the component of Y-axis, the computation time of the CORDIC algorithm is limited by its inherently sequential relationship. However, in CORDIC algorithm, the remaining rotation angle or Y- component are always required to approach to zero. The key idea of our approach is to separate the sign detection operation of remaining rotation angle or the component of Y- axis evaluation from the rotation operation. By taking the absolute values of these variables, the angle or Y-component iteration are fixed to subtraction operation. Therefore, we can successively subtract the residues without knowing the signs of preceding remaining rotation angle or the component of Y-axis, while their signs can be detected parallely, independently and in a pipelined fashion. Doing this way the sequential relationship of CORDIC algorithm between the computation of angle calculated and rotation operation is eliminated, and the time for the CORDIC operations can be greatly reduced. The corresponding CORDIC processor we proposed consists of regular pipelined slices. Each pipeline slice contains only one or two signed-digit adder and one digit level absoluter. Therefore, the duration of a clock cycle is very short, that is about two or three signed-digit adder delays. And iteration is completed within two or three clock cycles. Since the pipeline slice is regular, the CORDIC processor is well suited for VLSI implementation. The sequential architecture for rotation mode of CORDIC algorithm is realized by 0.8um CMOS technology to verify our design. The chip, which has 32-bit operand wordlength, is 6.2mm*5.3mm in area. It can operate at 10MHz clock frequency.