A 2.6-GByte/s multipurpose chip-to-chip interface Lau, B.; Yiu-Fai Chan; Moncayo, A. ...
IEEE journal of solid-state circuits,
1998-Nov., 1998-11-00, 19981101, Volume:
33, Issue:
11
Journal Article
Peer reviewed
A 2.6 GByte/s megacell that interfaces to single or double byte wide DRAMs or logic chips is implemented using 0.35-0.18 /spl mu/m CMOS technologies. Special I/O circuits are used to guarantee 800 ...Mbit/s/pin data rate. Microwave PC board design methodologies are used to achieve the maximum possible interconnect bandwidth.
We have measured the charge-state distributions of argon and potassium after ionization by photons with energies near the K-shell ionization threshold. Despite the similarity in core electron ...configurations, the two atoms show remarkable differences in the resulting distribution of ion charge states. The valence electron in potassium is rarely a spectator during core relaxation, and its presence enhances the loss of electrons excited into Rydberg levels or strongly reduces the recapture of slow photoelectrons during postcollision interaction.
A high-speed interface circuit delivering 660MB/s data is implemented as a byte-wide I/O bus-interface cell. The interface contains low-swing input receivers, controlled-current output drivers, and ...clock-recovery circuits. The circuits perform well in noisy environments such as microprocessors, and withstand LdI/dt noise generated in high-inductance packages such as PQFPs. The interface is implemented as a full-custom ASIC library megacell, reducing area and power over gate-array approaches. An advanced CAD methodology is used to easily port the analog circuits and high-speed digital circuits in the interface cell to multiple-fabrication process technologies. The cell is used as an interface for ASIC-to-DRAM communication and for ASIC-to-ASIC communication, for point-to-point links and for bused links.
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