The experiment BESIII, running at the accelerator BEPCII in Beijing (P.R.C.), is going to be updated with the replacement of the Inner Drift Chamber with a Cylindrical triple-GEM Inner Tracker ...(CGEM-IT). In the R&D stage, two standalone C++ codes were implemented: GTS (Garfield-based Triple-GEM Simulator), for digitization and tuning of simulated data to the experimental ones, and GRAAL (GEM Reconstruction And Analysis Library), for the reconstruction and analysis of the experimental events collected in testbeams. GTS simulates the triple-GEM response to the particle passage, treating each stage separately: ionization, GEM properties, gas mixture, magnetic field and finally the induction of the signal on the anode. The necessary information was extracted by GARFIELD++ simulations, parametrized and used as input in GTS. This speeds up the simulation, since GTS performs only samplings instead of the full digitization chain. The simulated events were reconstructed with the same procedure used for experimental data and tuning factors were evaluated to obtain a satisfactory match. GRAAL is used in the analysis of the testbeam experimental data. It provides several levels of reconstruction: from the cluster formation, gathering contiguous firing strips, to the spatial position and the signal time reconstruciton. Two algorithms are used: the charge centroid and the micro-TPC, which exploit the charge deposition on the strips and the time information. Also a merging of the two algorithms is available to efficiently weight the two outcomes and obtain the best estimate of the spatial coordinate. Moreover, GRAAL performs tracking and alignment. Both codes are going to be made available also for other MPGDs simulation and reconstruction.
Triple-GEM detectors are a well known technology in high energy physics. In order to have a complete understanding of their behavior, in parallel with on beam testing, a Monte Carlo code has to be ...developed to simulate their response to the passage of particles. The software must take into account all the physical processes involved from the primary ionization up to the signal formation, e.g. the avalanche multiplication and the effect of the diffusion on the electrons. In the case of gas detectors, existing software such as Garfield already perform a very detailed simulation but are CPU time consuming. A description of a reliable but faster simulation is presented here: it uses a parametric description of the variables of interest obtained by suitable preliminary Garfield simulations and tuned to the test beam data. It can reproduce the real values of the charge measured by the strip, needed to reconstruct the position with the Charge Centroid method. In addition, particular attention was put to the simulation of the timing information, which permits to apply also the micro-Time Projection Chamber position reconstruction, for the first time on a triple-GEM. A comparison between simulation and experimental values of some sentinel variables in different conditions of magnetic field, high voltage settings and incident angle will be shown.
Graphics Processing Units for HEP trigger systems Ammendola, R.; Bauce, M.; Biagioni, A. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
07/2016, Volume:
824
Journal Article
Peer reviewed
Open access
General-purpose computing on GPUs (Graphics Processing Units) is emerging as a new paradigm in several fields of science, although so far applications have been tailored to the specific strengths of ...such devices as accelerator in offline computation. With the steady reduction of GPU latencies, and the increase in link and memory throughput, the use of such devices for real-time applications in high-energy physics data acquisition and trigger systems is becoming ripe. We will discuss the use of online parallel computing on GPU for synchronous low level trigger, focusing on CERN NA62 experiment trigger system. The use of GPU in higher level trigger system is also briefly considered.
The LAUE project and its main results
Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE,
01/2013
Conference Proceeding
The authors describe a VLSI processor for pattern recognition based on content addressable memory (CAM) architecture, optimized for on-line track finding in high-energy physics experiments. A large ...CAM bank stores all trajectories of interest and extracts the ones compatible with a given event. This task is naturally parallelized by a CAM architecture able to output identified trajectories, searching for matches on 96-bit wide patterns, in just a few 40-MHz clock cycles. We have developed this device (called the AMchip03 processor) for the silicon vertex trigger (SVT) upgrade at the Collider Detector experiment at Fermilab (CDF) using a standard-cell VLSI design methodology. This approach provides excellent pattern density, while sparing many of the complexities and risks associated to a full-custom design. The cost/performance ratio is better by well more than one order of magnitude than an FPGA-based design. This processor has a flexible and easily configurable structure that makes it suitable for applications in other experimental environments. They look forward to sharing this technology
A commercial Graphics Processing Unit (GPU) is used to build a fast Level 0 (L0) trigger system tested parasitically with the TDAQ (Trigger and Data Acquisition systems) of the NA62 experiment at ...CERN. In particular, the parallel computing power of the GPU is exploited to perform real-time fitting in the Ring Imaging CHerenkov (RICH) detector. Direct GPU communication using a FPGA-based board has been used to reduce the data transmission latency. The performance of the system for multi-ring reconstrunction obtained during the NA62 physics run will be presented.
The NA62 experiment at the CERN-SPS is designed to study the K + → π + νν ultra-rare decay using a high intensity hadron beam and detecting its decay products. The lowest level (Level-0, L0) trigger ...processor represents a crucial component in reducing the event rate, estimated to be about 10 MHz for most of the sub-detectors which form the trigger, by a factor 10 with a maximum admitted latency of 1 ms. For the realization of the trigger selection, two different approaches were developed. A first project is fully based on FPGA, in which the whole logic for data selection is hardware programmed, while the second one joins an off-the-shelf PC to the FPGA for greater flexibility in trigger programming. Development, test results and performances during NA62 data taking will be presented.
PDF
