Stochastic variation of process parameters within a die and technology-limitation-driven variation from die-to-die give rise to unique distribution patterns for manufacturing process parameters. ...These patterns work as a process signature that is transferred from the device level to the system level through electrical circuits and can be used to make a distinction among the processes. In this work, we propose an in-situ manufacturing process technology distinction method', Radio Frequency Process Specific Functions (RF-PSF)', that uses process-specific inherent properties of an IC manifested in the transmitted radio frequency signal. Among many desirable testing criteria, RF-PSF addresses the question of fabrication with the intended process technology. This information plays an important role in modern zero-trust architecture and IC clone detection, a counterfeiting method where the IC is manufactured using a different process. An RF transmitter with RF-DAC power amplifier for QPSK modulation has been designed and simulated in 14nm, 22nm, and 65nm processes for 5 process corners (TT, FF, FS, SF, and SS) in Cadence. The simulated data have been processed in MATLAB. A Multilayer Perceptron (MLP), trained with the constellation data, provides an average accuracy of ~90% for process distinction. Realizing that (i) a higher order modulation will have even more process information and (ii) we can harness the Convolutional Neural Network's (CNN) improved capability on pattern recognition, we can feed image-like constellation plots to a CNN to get better and consistent performance. Using the baseband constellations for 64-QAM modulated data as images, we have achieved ~100% accuracy with commonly used, pretrained CNN models (ResNet18, ResNet50, and GoogleNet) through transfer learning. The separation among 5 process corners within a process, termed intra-process variation, is also analyzed. The effect of baseband sampling rate and ADC resolution, two practical limitations in RF systems, have been explored. An extensive study has been performed on the effect of a key design parameter at the RF circuit level i.e. W/L or aspect ratio, leading to design insights, proper CNN selection, and some control parameters. This work establishes RF-PSF as a zero-power, zero-area overhead, in-situ process distinction method.
A dc-20-GHz multiple-return-to-zero digital-to-analog converter (DAC) is proposed for direct radio frequency synthesis. To minimize frequency-dependent amplitude and phase errors in the output ...summing node, which can dominate linearity performance at GHz and mm-wave frequencies, a vertically stacked tree (VST) and feed-forward (FF) path are proposed. While the VST minimizes variation in frequency response among the MSB cells, the FF path improves matching between the MSBs and LSBs, providing up to 21-dB improvement in simulated spurious-free dynamic range (SFDR) at 20 GHz. To account for additional errors introduced by process variation, the DAC utilizes per-cell calibration of both amplitude and timing. The DAC is implemented in a 0.13-μm SiGe process with an area of 6.25 mm 2 and consumes 1.91 W. After amplitude and timing calibration, >48-dB SFDR and lesser than -46 dBc intermodulation distortion are achieved from dc to 20 GHz.
A power and area efficient, capacitively coupled receiver for short links is presented. The proposed architecture enables a wide input common-mode range by utilizing on-chip ac-coupling capacitors, ...which avoids the use of large, off-chip capacitors or slow, rail-to-rail input stages. The small coupling capacitance and bias switches generate a pseudo return-to-zero pulse that is latched into the receiver via digital feedback. This input latching reduces the effects of baseline wander caused by unbalanced data streams without the need for encoding or scrambling. In addition, the full-scale digital feedback is used as the receiver output, enabling direct interface with standard digital cells. The architecture is implemented in a 130-nm SiGe BiCMOS and 45-nm CMOS silicon-on-insulator (SOI) technology. The 130-nm SiGe BiCMOS design achieves a peak data rate of 10 Gb/s at 5.1 mW, while a peak efficiency of 0.46 mW/Gb/s is recorded at 8 Gb/s. The 45-nm CMOS SOI design achieves a peak data rate of 30 Gb/s at 12.02 mW, with a peak efficiency of 0.24 mW/Gb/s at 25 Gb/s. Both the SiGe BiCMOS and CMOS SOI designs exhibit BERs of <10<inline-formula> <tex-math notation="LaTeX">^{-12} </tex-math></inline-formula> with PRBS15 data as small as 100 mV and occupy 0.012 and 0.007 mm 2 , respectively, including the on-chip coupling capacitance.
This paper presents a highly linear BiCMOS sample and hold amplifier (SHA) providing 2.8-GS/s intermediate frequency (IF) sampling for a 1-GHz input bandwidth spanning from 1.5 to 2.5 GHz. A ...single-transistor hold-mode feedthrough cancellation technique is implemented to remove distortion resulting from the nonlinear parasitic capacitance at the sampling node. The SHA is designed in a mainstream 130-nm BiCMOS technology using SiGe heterojunction bipolar transistors to buffer and sample the wideband input. The proposed SHA enables monolithic integration with a high-speed analog-to-digital converter core to realize a high-performance converter solution. This independent sampling front end occupies a core chip area of 0.6 mm 2 and consumes an average power of 1.26 W. The SHA is a pseudo-differential open-loop design that includes two cascaded track-and-hold amplifiers, a high-speed clock driver, and externally adjustable current mirror biases. The high-speed clock drivers and buffers add 170 mW to the total power consumption. The measurements of the fabricated SHA show a 10-bit effective resolution across the 1-GHz IF bandwidth and < −61-dBc HD 2 and HD 3 .
A multimode delta-sigma (Formula Omitted) RF digital-to-analog converter (RF-DAC) is proposed for direct digital-to-RF synthesis. The proposed circuit uses a single clock frequency (Formula ...Omitted) and provides a Formula Omitted modulator (DSM) that operates in bandpass (BP) and highpass (HP) modes to synthesize signals around Formula Omitted, Formula Omitted, or Formula Omitted. The on-chip 14 bit second-order DSM implements an array of 1 bit pipelined subtract functions to generate 3 bit Formula Omitted rate RF-DAC input data. Analog interleaving via a second 3 bit DAC is used to reject the first DAC image, simultaneously doubling the usable bandwidth of the HP DSM and increasing the SNR. Calibration circuits are added to the DAC to compensate for amplitude and timing variations. The proposed RF-DAC is implemented in 130 nm SiGe BiCMOS with an area of Formula Omitted. Measurements at Formula Omitted yield an output power of Formula Omitted with 76.2 dB signal-to-image-rejection ratio (SIRR), 76.2 dB SFDR over a 100 MHz bandwidth, Formula Omitted IM3, Formula Omitted WCDMA ACLR, and Formula Omitted LTE ACLR. Changing Formula Omitted to 3 GHz allows frequencies of 2.25 GHz to be generated with output power of Formula Omitted, 65.2 dB SFDR, Formula Omitted, Formula Omitted WCDMA ACLR, and Formula Omitted LTE ACLR.
Abstract The most commonly reported complications related to cementless hip stems are loosening and thigh pain; both of these have been attributed to high levels of relative micromotion at the ...bone–implant interface due to insufficient primary fixation. Primary fixation is believed by many to rely on achieving a sufficient interference fit between the implant and the bone. However, attempting to achieve a high interference fit not infrequently leads to femoral canal fracture either intra-operatively or soon after. The appropriate range of diametrical interference fit that ensures primary stability without risking femoral fracture is not well understood. In this study, a finite element model was constructed to predict micromotion and, therefore, instability of femoral stems. The model was correlated with an in vitro micromotion experiment carried out on four cadaver femurs. It was confirmed that interference fit has a very significant effect on micromotion and ignoring this parameter in an analysis of primary stability is likely to underestimate the stability of the stem. Furthermore, it was predicted that the optimal level of interference fit is around 50 μm as this is sufficient to achieve good primary fixation while having a safety factor of 2 against femoral canal fracture. This result is of clinical relevance as it indicates a recommendation for the surgeon to err on the side of a low interference fit rather than risking femoral fracture.
Elongation of arthroscopically tied knots Mishra, D K; Cannon, Jr, W D; Lucas, D J ...
The American journal of sports medicine,
1997 Jan-Feb, Volume:
25, Issue:
1
Journal Article
Peer reviewed
It has been postulated that some arthroscopic shoulder stabilization failures may be due to knot slippage. In an effort to improve arthroscopic technique, we performed tensile testing on four ...arthroscopically tied knots with two commonly used suture materials. Handtied square knots served as controls. Sutures of No. 1 Maxon and No. 1 Ticron were used. Four types of sliding knot configurations were tested: the overhand loop, the Duncan loop, the Roeder knot, and the Snyder knot. Knots were tied via a knot pusher, and testing was performed in a normal saline-filled thermoplastic chamber. Knots were tied around two rings connected to a Bionix 858 materials testing apparatus. The knots were tested under conditions of cyclic loading and loading to failure. Results of the testing revealed that the most important factor in knot security was the type of suture material, although there were differences with the type of knot. With the Maxon suture, there was significantly decreased ultimate failure load of all of the arthroscopically tied knots compared with handtied square knots. Knots tied with Ticron were similar in strength for both arthroscopically and handtied groups. The surgeon who chooses a monofilament absorbable suture should be aware that a high percentage of knots fail under low load cyclic testing, and that all of these knots were inferior to handtied square knot controls in testing to failure.
A multimode delta-sigma (ΔΣ) RF digital-to-analog converter (RF-DAC) is proposed for direct digital-to-RF synthesis. The proposed circuit uses a single clock frequency (f 8 ) and provides a ΔΣ ...modulator (DSM) that operates in bandpass (BP) and highpass (HP) modes to synthesize signals around f 8 /4, f 8 /2, or 3f 8 /4. The on-chip 14 bit second-order DSM implements an array of 1 bit pipelined subtract functions to generate 3 bit f8 rate RF-DAC input data. Analog interleaving via a second 3 bit DAC is used to reject the first DAC image, simultaneously doubling the usable bandwidth of the HP DSM and increasing the SNR. Calibration circuits are added to the DAC to compensate for amplitude and timing variations. The proposed RF-DAC is implemented in 130 nm SiGe BiCMOS with an area of 0.563 mm 2 . Measurements at f 8 = 2 GHz yield an output power of -0.6 dBm with 76.2 dB signal-to-image-rejection ratio (SIRR), 76.2 dB SFDR over a 100 MHz bandwidth, -80 dBc IM3, -67.2 dB WCDMA ACLR, and -66.4 dBc LTE ACLR. Changing f 8 to 3 GHz allows frequencies of 2.25 GHz to be generated with output power of -16.6 dBm, 65.2 dB SFDR, -62 dBc IM3, -59.3 dB WCDMA ACLR, and -59.2 dBc LTE ACLR.
Recent trends in 5G and radar systems have revealed the need for high-frequency DACs with minimal spurious emissions. Amplitude and timing errors in the DAC have proven to be a significant hindrance ...to linearity performance and have an increasing impact with frequency. Primary contributors to these errors are impedance mismatches in the current combining network as well as device mismatches. This work presents a frequency-domain approach to SFDR analysis in which the contribution of each individual cell on the output spectrum is analyzed and errors are applied as transfer functions in the frequency domain. Using this method, static amplitude and timing errors can be examined through a Monte Carlo (MC) analysis using only numerical computation, thus eliminating the need to run a transient simulation for each MC sample. Moreover, unlike the conventional analysis, the frequency-domain approach is amenable to the small-signal models produced by EM simulations, enabling the incorporation of complex output summing node structures with little impact to simulation time and convergence. The frequency-domain analysis is used to produce a 10-bit 3.35 Gsps MRZ DAC capable of synthesizing frequencies from DC to 20 GHz with greater than 48 dB} SFDR. The design includes a vertically-stacked tree (VST) interconnect structure that minimizes attenuation and phase mismatches in the output summing node. Additionally, a per-cell timing adjustment circuit is proposed, which, along with static current calibration, is used to minimize the remaining errors. Measurement results show that the calibration provides up to 7 dB improvement in SFDR at 20 GHz. The combination of the VST and calibration techniques yield the highest reported SFDR at 20 GHz, while synthesizing the highest instantaneous bandwidth among RF DACs.
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