The ATLAS Pixel Insertable B-layer (IBL) Huegging, F
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
09/2011, Volume:
650, Issue:
1
Journal Article
Peer reviewed
Open access
The ATLAS Detector will be upgraded for higher intensity running of the LHC. A long shutdown is envisioned in 2016 prior to the so-called Phase I running. A new pixel layer, called the Insertable ...B-Layer (IBL), will be inserted at a radius of about 3.2
cm between the existing Pixel Detector and a new (smaller radius) beam-pipe. The IBL requires the development of several new technologies to cope with the increased radiation level and pixel occupancy, as well as to improve the physics performance of the existing Pixel Detector. The IBL project provides a test of technologies for the Phase II upgrade of the entire ATLAS tracker for luminosities around 10
35
cm
−2
s
−1. An overview of the project with particular emphasis on the IBL layout and expected performance as well as the module development including hybridization technologies is presented.
The insertable B-Layer upgrade of the ATLAS pixel detector forsees the installation of a fourth pixel layer close to the beam pipe inside the current ATLAS pixel detector. A new readout chip (FE-I4) ...has been developed to match the increased requirements in terms of radiation hardness and hit occupancy. A new USB-based test system for ATLAS hybrid pixel detectors (USBpix) will serve as test bench for this new readout chip generation. The performance of USBpix is compared to the performance of the TPLL/TPCC system, used for testing the ATLAS pixel detector readout chips FE-I3 and modules. The main differences between the FE-I3 and the FE-I4 are summarized from the point of view of the test systems and the implementation of the main blocks for chip configuration, data storage and histogramming in the USBpix FPGA firmware for both chip generations is discussed. Results of the first measurements which were done using the FE-I4 emulator developed for debugging purposes are discussed.
Reducing material in silicon trackers is of major importance for a good detector performance overall, and poses a big challenge in the development of the detectors. To match the low material ...desirable for trackers in High Energy Physics experiments at upgraded luminosities, special techniques have to be developed to address the main sources of material, i.e. mechanical structure and services, and to prevent new significant contributions to the detector material coming for instance from larger Front-End chips. In this framework three methods are developed to reduce the material added by services and electronics: (1) serial powering, (2) light weight aluminum flex cables and Through Silicon Vias, and (3) thin Front-End chips. The methods are presented in this paper using the upgrades of the ATLAS pixel detector as an example of application.
3D technologies are investigated for the upgrade of the ATLAS pixel detector at the HL-LHC. R&D focuses on both, IC design in 3D, as well as on post-processing 3D technologies such as Through Silicon ...Via (TSV). The first one uses a so-called via first technology, featuring the insertion of small aspect ratio TSV at the pixel level. As discussed in the paper, this technology can still present technical challenges for the industrial partners. The second one consists of etching the TSV via last. This technology is investigated to enable 4-side abuttable module concepts, using today's pixel detector technology. Both approaches are presented in this paper and results from first available prototypes are discussed.
In this paper we discuss results relevant to 3D Double-Side Double Type Column (3D-DDTC) pixel sensors fabricated at FBK (Trento, Italy) and oriented to the ATLAS upgrade. Some assemblies of these ...sensors featuring different columnar electrode configurations (2, 3, or 4 columns per pixel) and coupled to the ATLAS FEI3 read-out chip were irradiated up to large proton fluences and tested in laboratory with radioactive sources. In spite of the non-optimized columnar electrode overlap, sensors exhibit reasonably good charge collection properties up to an irradiation fluence of 2×1015neqcm−2, while requiring bias voltages in the order of 100V. Sensor operation is further investigated by means of TCAD simulations which can effectively explain the basic mechanisms responsible for charge loss after irradiation.
3D silicon pixel sensors: Recent test beam results Hansson, P.; Balbuena, J.; Barrera, C. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
02/2011, Volume:
628, Issue:
1
Journal Article
Peer reviewed
The 3D silicon sensors aimed for the ATLAS pixel detector upgrade have been tested with a high energy pion beam at the CERN SPS in 2009. Two types of sensor layouts were tested: full-3D assemblies ...fabricated in Stanford, where the electrodes penetrate the entire silicon wafer thickness, and modified-3D assemblies fabricated at FBK-irst with partially overlapping electrodes. In both cases three read-out electrodes are ganged together to form pixels of dimension
50
×
400
μ
m
2
. Data on the pulse height distribution, tracking efficiency and resolution were collected for various particle incident angles, with and without a 1.6
T magnetic field. Data from a planar sensor of the type presently used in the ATLAS detector were used at the same time to give comparison.
The radiation hardness of passive CMOS pixel sensors fabricated in 150nm LFoundry technology is investigated. CMOS process lines are especially of interest for large-scale silicon detectors as they ...offer high production throughput at comparatively low cost. Moreover, several features like poly-silicon resistors, MIM-capacitors and several metal layers are available which can help enhance the sensor design. The performance of a 100µm thin passive CMOS sensor with a pixel pitch of 50µm at different irradiation levels, 5 × 1015neqcm−2 and 1 × 1016neqcm−2, is presented. The sensor was bump-bonded and read out using the RD53A readout chip. After the highest fluence a hit-detection efficiency larger than 99% is measured for minimum ionising particles. The measured equivalent noise charge is comparable to conventional planar pixel sensors. Passive CMOS sensors are thus an attractive option for silicon detectors operating in radiation harsh environments like the upgrades for the LHC experiments.
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