Interconnect tuning is an increasingly critical degree of freedom in the physical design of high-performance VLSI systems. By interconnect tuning, we refer to the selection of line thicknesses, ...widths and spacings in multi-layer interconnect to simultaneously optimize signal distribution, signal performance, signal integrity, and interconnect manufacturability and reliability. This is a key activity in most leading-edge design projects, but has received little attention in the literature. Our work provides the first technology-specific studies of interconnect tuning in the literature. We center on global wiring layers and interconnect tuning issues related to bus routing, repeater insertion, and choice of shielding/spacing rules for signal integrity and performance. We address four basic questions. (1) How should width and spacing be allocated to maximize performance for a given line pitch? (2) For a given line pitch, what criteria affect the optimal interval at which repeaters should be inserted into global interconnects? (3) Under what circumstances are shield wires the optimum technique for improving interconnect performance? (4) In global interconnect with repeaters, what other interconnect tuning is possible? Our study of question (4) demonstrates a new approach of offsetting repeater placements that can reduce worst-case cross-chip delays by over 30% in current technologies.
The traditional analysis of signal delay in a transmission line begins with a lossless LC representation, which yields a wave equation governing the system response; 2-port parameters are typically ...derived and the solution is obtained in the transform domain. In this paper, we begin with a distributed RC line model of the interconnect and analytically solve the resulting diffusion equation for the voltage response. A new closed form expression for voltage response is obtained by incorporating appropriate boundary conditions for interconnect delay analysis. Calculations of 50% and 90% delay times for various cases of interest (e.g., open-ended RC line) give substantially different estimates from those commonly cited in the literature, thus suggesting revised delay estimation methodologies and intuitions for the design of VLSI interconnects. The discussion furthermore provides a unifying treatment of the past three decades of RC interconnect delay analyses.
Phys. Rev. E 94, 062307 (2016) $k$-Core percolation has served as a paradigmatic model of discontinuous
percolation for a long time. Recently it was revealed that the order parameter
of $k$-core ...percolation of random networks additionally exhibits critical
behavior. Thus $k$-core percolation exhibits a hybrid phase transition. Unlike
the critical behaviors of ordinary percolation that are well understood, those
of hybrid percolation transitions have not been thoroughly understood yet.
Here, we investigate the critical behavior of $k$-core percolation of
Erd\H{o}s-R\'enyi networks. We find numerically that the fluctuations of the
order parameter and the mean avalanche size diverge in different ways. Thus, we
classify the critical exponents into two types: those associated with the order
parameter and those with finite avalanches. The conventional scaling relations
hold within each set, however, these two critical exponents are coupled.
Finally we discuss some universal features of the critical behaviors of
$k$-core percolation and the cascade failure model on multiplex networks.
Signoff timing analysis remains a critical element in the IC design flow. Multiple signoff corners, libraries, design methodologies, and implementation flows make timing closure very complex at ...advanced technology nodes. Design teams often wish to ensure that one tool's timing reports are neither optimistic nor pessimistic with respect to another tool's reports. The resulting "correlation" problem is highly complex because tools contain millions of lines of black-box and legacy code, licenses prevent any reverse-engineering of algorithms, and the nature of the problem is seemingly "unbounded" across possible designs, timing paths, and electrical parameters.
In this work, we apply a "big-data" approach to the timer correlation problem. We develop a machine learning-based tool, Golden Timer eXtension (GTX), to correct divergence in flip-flop setup time, cell arc delay, wire delay, stage delay, and path slack at timing endpoints between timers. We propose a methodology to apply GTX to two arbitrary timers, and we evaluate scalability of GTX across multiple designs and foundry technologies/libraries, both with and without signal integrity analysis. Our experimental results show reduction in divergence between timing tools from 139.3ps to 21.1ps (i.e., 6.6×) in endpoint slack, and from 117ps to 23.8ps (4.9× reduction) in stage delay. We further demonstrate the incremental application of our methods so that models can be adapted to any outlier discrepancies when new designs are taped out in the same technology/library. Last, we demonstrate that GTX can also correlate timing reports between signoff and design implementation tools.
A hybrid phase transition (HPT) that exhibits properties of continuous and discontinuous phase transitions at the same transition point has been observed in diverse complex systems. Previous studies ...of the HPTs on complex networks mainly focused on whether the order parameter is continuous or discontinuous. However, more careful and fundamental questions on the critical behaviors of the HPT such as how the divergences of the susceptibility and of the correlation size are affected by the discontinuity of the order parameter have been addressed. Here, we consider a generalized epidemic model that is known to exhibit a discontinuous transition as a spinodal transition. Performing extensive numerical simulations and using finite-size scaling analysis, we examine diverging behaviors of the susceptibility and the correlation size. We find that when there is one infectious node and under a certain condition, the order parameter can exhibit a discontinuous jump but does not exhibit any critical behavior before or after the jump. This feature differs from what we observed in HPTs in the percolation pruning process. However, critical behavior appears in the form of a power-law behavior of the outbreak size distribution. The mean outbreak size, corresponding to the susceptibility, diverge following the conventional percolation behavior. Thus a mixed-order transition occurs. The hyperscaling relation does not hold.
3D integrated circuits (3DICs) with through-silicon vias (TSVs) are an important direction for semiconductor-based products and "More than Moore" scaling. However, 3DICs bring simultaneous challenges ...of reliability (power and temperature in stacks of thinned die) as well as variability (performance and power) in advanced technology nodes. In this paper, we study variability-reliability interactions and optimizations in 3DICs. Initial motivating studies show that in the presence of manufacturing variability, different die stacking orders can lead to as much as 2 years (~44%) difference in MTTF of a 3DIC stack. We study MTTF-driven die-stacking optimization with consideration of variability, and propose a "rule-of-thumb" guideline for stacking optimization to improve peak temperature as well as reliability in 3DICs. We also propose integer-linear programming (ILP) methods for reliability-driven die-stacking optimization. Our methods can achieve ~7% and ~28% improvement in average and minimum MTTF, respectively, of 3DICs; we also achieve ~3% improvement in performance under fixed reliability constraints. Our stacking optimizations can help improve 3DIC product yields under reliability requirements. Our research also yields the notable observation that a limited amount of manufacturing variation can "help" improve 3DIC product reliability when die-stacking optimization is applied.
We perform Monte Carlo simulations on stochastic models such as the Wolf-Villain (WV) model and the Family model in a modified version to measure the mean separation l between islands in a ...submonolayer regime and the damping time t* of layer-by-layer growth oscillations in one dimension. The stochastic models are modified, allowing for diffusion within interval r upon deposition. It is found numerically that the mean separation and the damping time depend on the diffusion interval r, leading to the fact that the damping time is related to the mean separation as t* approximately l(4/3) for the WV model and t* approximately l(2) for the Family model. The numerical results are in excellent agreement with recent theoretical predictions.
To reduce time and effort in IC implementation, fundamental challenges must be solved. First, the need for (expensive) humans must be removed wherever possible. Humans are skilled at predicting ...downstream flow failures, evaluating key early decisions such as RTL floorplanning, and deciding tool/flow options to apply to a given design. Achieving human-quality prediction, evaluation and decision-making will require new machine learning-centric models of both tools and designs. Second, to reduce design schedule, focus must return to the long-held dream of single-pass design. Future design tools and flows that never require iteration (i.e., that never fail, but without undue conservatism) demand new paradigms and core algorithms for parallel, cloud-based design automation. Third, learning-based models of tools and flows must continually improve with additional design experiences. Therefore, the EDA and design ecosystem must develop new infrastructure for ML model development and sharing.
PDF
