Catalytic chemical vapor deposition (Cat-CVD) can produce amorphous silicon (a-Si) films with low film stress, in general, compared to plasma-enhanced CVD, and is thus suited for the preparation of ...precursor a-Si films for thick poly-Si films applied for solar cells. The stress of a-Si films is known to sometimes play an important role for the crystallization of a-Si films and resulting grain size of polycrystalline Si (poly-Si) films formed. I investigate the impact of the stress of Cat-CVD a-Si films on the mechanism of explosive crystallization (EC) induced by flash lamp annealing (FLA). The stress of Cat-CVD a-Si films can be controlled by changing the temperatures of substrates and/or a catalyzing wire during film deposition. Cat-CVD a-Si films with tensile stress (~200MPa) can be deposited as well as films with compressive stress. The enlargement of grain size is observed in a part of flash-lamp-crystallized (FLC) poly-Si films formed from Cat-CVD films with tensile stress compared to those with compressive stress, which might be an indication of a certain degree of impact of film stress on poly-Si formation. The grain size is, however, much smaller than that of FLC poly-Si films formed from electron-beam- (EB-) evaporated a-Si films with similar tensile stress. This fact may indicate the existence of other critical determinants of EC mechanism.
•A typical degradation was seen in a cell-level potential-induced degradation test.•The test has different temperature dependence from that in module-level tests.•The difference is related to ...temperature-dependent contact resistances in samples.•The difference can be reduced by increasing pressure applied to the samples.
The degradation behavior of crystalline silicon (c-Si) solar cells in a cell-level potential-induced degradation (PID) test and the effect of the test conditions are reported. The PID tests were performed in a vacuum chamber by applying a voltage of 1000V from a temperature-controlled aluminum chuck underneath an unlaminated sample stack to the top copper electrode placed on the stack. The stack was composed of soda-lime glass, an ethylene vinyl-acetate copolymer sheet, and a conventional p-type c-Si solar cell. The investigated solar cell exhibited a large degradation of the fill factor and slight degradation of the open-circuit voltage. These degradations were mainly caused by a reduction in the parallel resistance, which is the same degradation behavior as that reported previously. This indicates that the cell-level PID test well reproduces the typical degradation behavior. However, the leakage current in the unlaminated sample stack at a relatively low temperature exhibited a different temperature dependence from that in a laminated sample stack. The difference in the temperature dependence was caused by temperature-dependent contact resistances within the unlaminated sample stacks. This indicates that there is a difference between the temperature dependences in cell-level and module-level PID tests. This difference in the temperature dependence was reduced by the use of a heavier top electrode. These findings may assist in choosing the proper test conditions for this kind of cell-level PID test. A cell-level PID test for an n-type front-emitter c-Si solar cell was also performed. A typical degradation behavior, characterized by reductions in the open-circuit voltage and the short-circuit current, was observed, which implies that this test can be widely applied to PID phenomena occurring in many kinds of solar cells.
Accelerated tests were used to study potential‐induced degradation (PID) in photovoltaic (PV) modules fabricated from silicon heterojunction (SHJ) solar cells containing tungsten‐doped indium oxide ...(IWO) transparent conductive films on both sides of the cells and a rear‐side emitter. A negative bias of −1000 V was applied to a module with respect to the cover glass surface in a chamber maintained at 85°C, which significantly reduced the cell's short‐circuit current density (Jsc) within several days. Based on dark current density‐voltage and external quantum efficiency measurements, the reduction in the Jsc was attributed to optical losses rather than carrier recombination. X‐ray absorption fine structure spectroscopy showed the formation of metallic indium (In) in the IWO layers of a degraded cell, which suggests that the root cause of the optical loss was a darkening of the front IWO layers caused by the precipitation of metallic In. In extremely severe PID tests, the SHJ PV modules exhibited not only a further reduction in the Jsc but also a moderate reduction in the open‐circuit voltage (Voc). These Jsc and Voc reductions were probably caused by sodium being introduced into the base region of the cells. A comparison of the PID test results of the SHJ PV modules with those of other types of PV modules indicates that SHJ PV modules have a relatively high resistance to PID. As a module with an ionomer encapsulant exhibited little degradation, their high resistances to PID may be further improved by using encapsulants with high electrical resistances.
Here, we comprehensively investigated potential‐induced degradation (PID) occurring in photovoltaic modules fabricated from silicon heterojunction cells containing tungsten‐doped indium oxide transparent conductive films on both sides of the cells and a rear‐side emitter. It was found that under negative bias, the silicon heterojunction photovoltaic modules undergo PID characterized by a reduction in the short‐circuit current densities. The root cause of this PID was the darkening of the front tungsten‐doped indium oxide layers caused by the formation of metallic indium precipitates.
This letter deals with the potential-induced degradation (PID) of silicon heterojunction (SHJ) photovoltaic (PV) modules. After rapid indoor PID tests applying a voltage of -1000 V at 85 °Celsius, ...the modules exhibited a significant reduction in short-circuit current density (Jsc). On the other hand, the dark current density-voltage characteristics of the modules were intact after the PID tests, indicating that the reduction in Jsc is attributed not to carrier recombination but to optical loss. A degraded module slightly recovered its performance loss upon applying a positive bias but complete recovery was not observed, showing that the PID of SHJ PV modules is not reversible. A module with an ionomer encapsulant showed high PID resistance, revealing that the degradation of SHJ PV modules can be prevented by the use of ionomer encapsulants.
We investigated the influence of indium tin oxide (ITO) sputtering damage to various types of amorphous silicon (a-Si) passivation films deposited by catalytic chemical vapor deposition. Intrinsic ...(i-) a-Si, n-type (n-) a-Si/i-a-Si, and p-type (p-) a-Si/i-a-Si stacked films were prepared on crystalline Si, and ITO was sputtered at various temperatures and RF powers, followed by post-annealing at 200°C. Effective minority carrier lifetime (τeff) of almost all the samples decreases drastically after sputtering, while τeff of the samples with ITO sputtered at room temperature recovers significantly by post-annealing. Annealing before sputtering and sputtering at lower RF power leads to more effective recovery of τeff. The samples with ITO sputtered to an n-a-Si/i-a-Si stack show large τeff recovery, while the samples with ITO sputtered to a p-a-Si/i-a-Si stack show much smaller τeff recovery. τeff recovery after ITO sputtering thus depends on the types of a-Si passivation films, which may be related to the modification of band alignment by the existence of ITO.
This study addresses the behavior of n-type front-emitter (FE) crystalline-silicon (c-Si) photovoltaic (PV) modules in potential-induced degradation (PID) tests with a long duration of up to 20 days. ...By PID tests where a negative bias of −1000 V was applied at 85 °C to 20 × 20-mm2-sized n-type FE c-Si PV cells in modules, the short-circuit current density (Jsc) and the open-circuit voltage (Voc) started to be decreased within 10 s, and strongly saturates within approximately 120 s, resulting in a reduction in the maximum output power (Pmax) and its saturation. After the saturation, all the parameters were almost unchanged until after 1 h. However, the fill factor (FF) then started to decrease and saturated again. After approximately 48 h, FF further decreased again, accompanied by a reduction in Voc. The first degradation is known to be due to an increase in the surface recombination of minority carriers by the accumulation of additional positive charges in the front Si nitride (SiNx) films. The second and third degradations may be due to significant increases in recombination in the space charge region. The enhancement in recombination in the space charge region may be due to additional defect levels of sodium (Na) introduced into the space charge region in the p–n junction. We also performed recovery tests by applying a positive bias of +1000 V. The module with the first degradation completely recovered its performance losses, and the module with the second degradation was almost completely recovered. On the contrary, the modules with the third degradation could not be recovered. These findings may improve the understanding of the reliability of n-type FE c-Si PV modules in large-scale PV systems.
•n-Type front-emitter c-Si PV modules undergo three-stage degradations by long-term PID tests.•The first degradation is due to an increase in surface recombination.•The second and third degradations may be due to significant increases in recombination currents.•The degree of performance recovery strongly depends on that of degradation.
Flash lamp annealing (FLA) of micrometre-order thick amorphous silicon (a-Si) films can induce explosive crystallization (EC), high-speed lateral crystallization driven by the release of latent heat. ...We develop multi-pulse FLA system, which emits a quasi-millisecond pulse consisting of a number of subpulses. The emission frequency of the subpulses can be systematically controlled, and the emission of subpulses leads to the periodic modulation of the temperature of a Si film and the resulting formation of macroscopic stripe patterns. The relationship between a subpulse emission frequency and the width of the macroscopic stripe patterns yields EC velocity. Two kinds of EC modes can be observed, depending on the methods of precursor a-Si deposition and (or) a-Si film thickness.
We have succeeded the formation of polycrystalline silicon (poly-Si) films by flash lamp annealing (FLA) of 4-μm-thick intrinsic amorphous silicon (a-Si(i)) films deposited directly on flat glass ...substrates by tuning catalytic chemical vapor deposition conditions. The use of a-Si(i) films deposited without intentional substrate heating leads to the suppression of Si film peeling during FLA. The a-Si(i) films deposited at room temperature have low film density, low film stress, and high defect density, compared to a-Si(i) films deposited at higher temperatures. The prevention of Si film peeling may be due to the low film stress and/or the suppression of the emergence of lateral explosive crystallization by using a-Si(i) films with low film density.
•We formed poly-Si films directly on glass substrates by FLA without film peeling.•The deposition temperature of Cat-CVD a-Si films is systematically controlled.•a-Si films deposited at room temperature do not peel off after FLA.•The suppression of Si film peeling may be due to low film stress and/or density.
Herein, ultrathin Al‐doped SiOx layer formed by immersing in Al(NO3)3 aqueous solution is introduced. This layer enables high‐level surface passivation with a maximum effective surface recombination ...velocity (Seff,max) < 16 cm s−1 at an excess carrier density (Δn) of 1 × 1015 cm−3 for 2.5 Ω cm n‐type c‐Si without any other processes such as film deposition in a vacuum chamber, high‐temperature annealing, and hydrogenation. This passivation effect presumably comes from negative fixed charges localized in Al‐doped SiOx layers, forming inversion layers due to upward Si band bending at the SiOx/Si interface. In addition, the Al‐doped SiOx layers facilitate accumulated holes at the interface to tunnel through the layers even though the applied bias is extremely low. The high tunnel current density of holes accumulated in the inversion layers implies that these ultrathin Al‐doped SiOx layers are expected to be favorably implemented for high‐efficiency passivating‐contact c‐Si solar cells.
Herein, ultrathin Al‐doped SiOx layer formed by immersing in Al(NO3)3 aqueous solution is introduced for high‐efficiency passivating‐contact c‐Si solar cells. This layer enables high‐level surface passivation with a maximum effective surface recombination velocity (Seff,max) < 16 cm s−1 and also facilitates accumulated holes at the interface to tunnel through the layers.
Indium tin oxide (ITO) film is the most widely used as front electrodes in solar cells with a copper metallization scheme. No work has focused on the barrier properties of the ITO layer on the ...textured silicon for solar cells. In this work, a thin indium tin oxide barrier layer and copper metal layer were deposited on textured (001) silicon by a sputtering. The stacks present Cu/ITO/Si. The structures of Cu/ITO/Si characterized by scanning transmission electron microscope, energy-dispersive X-ray spectrometer, and powder X-ray diffraction. The results show that the stacks of Cu/ITO/Si can be preserved up to 600 °C. The 35-nm thickness ITO layer was found to be a diffusion barrier against Cu up to 600 °C. The copper thin films were agglomerated and formed the particle at a temperature of 700 °C. The failure of Cu/ITO/Si can be attributed to agglomerate copper thin films and breakdown of ITO thin films at a temperature of 700 °C.
PDF
