Recent innovations in software defined CMOS radio transceiver architectures heavily rely on high-linearity switched-RC sampler and passive-mixer circuits, driven by digitally programmable multiphase ...clocks. Although seemingly simple, the frequency domain analysis of these linear periodically time variant (LPTV) circuits is often deceptively complex. This paper uses the properties of sampled LPTV systems and the adjoint (inter-reciprocal) network to greatly simplify the analysis of the switched-RC circuit. We first derive the transfer function of the equivalent linear time-invariant filter relating the input to the voltage sampled on the capacitor in the switched-RC kernel. We show how a leakage resistor across the capacitor can be easily addressed using our technique. A signal-flow graph is then developed for the complete continuous-time voltage waveform across the capacitor, and simplified for various operating regions. We finally derive the noise properties of the kernel. The results we derive have largely been reported in prior works, but the use of the adjoint network simplifies the derivation, while also providing circuit insight.
We present a low power analog adaptive equalization technique suitable for combating inter-symbol-interference at very high data rates. The proposed technique, which we term the lumped parameter ...equalizer, addresses several of the problems associated with conventional microwave equalizers based on the tapped delay line structure. The theory is given, and simulation results comparing it with the performance of ideal tapped delay line filters are shown. Circuit implementations are discussed, along with the effect of nonidealities on equalizer performance.
CMOS fixed-<inline-formula> <tex-math notation="LaTeX">g_{m} </tex-math></inline-formula> bias circuits are, as the name suggests, those that generate a bias current which keeps the transconductance ...of a MOS transistor equal to a constant (off-chip) conductance. Such circuits are useful in many analog and mixed-signal subsystems like filters and data-converters. This brief derives the textbook fixed-<inline-formula> <tex-math notation="LaTeX">g_{m} </tex-math></inline-formula> bias circuit from first principles, and shows these ideas can be used to generate alternative circuits.
We examine noise due to clock jitter in single-loop low-pass continuous-time delta-sigma (Delta Sigma) modulators (CT-DSMs) employing nonreturn to zero (NRZ) feedback digital-to-analog converters ...(DACs). Using the discrete-time version of the Bode sensitivity integral, we derive a lower bound on jitter noise and its relationship to the noise transfer function (NTF) of the modulator. We show that NTFs with optimized zeros result in lower jitter noise than those with all zeros at the origin. We give intuition to a recent observation (arrived through numerical optimization) that NTFs with peaking in their passbands have lower jitter noise than maximally flat NTFs. We propose a design procedure that minimizes the sum of the quantization and jitter noise. The arguments regarding Delta Sigma analog-to-digital converters are extended to Delta Sigma DACs and measurement results are presented.
We present a simple, intuitive technique to compensate the loop filter transfer function for excess delay in low-pass continuous-time DeltaSigma modulators. Conventional methods of finding the ...appropriate filter coefficients to account for loop delay work in the z -domain, leading to cumbersome algebra. We show that the same objective can be accomplished entirely in the continuous-time domain, resulting in a procedure that lends itself to hand calculations, even for high order modulators. We derive closed-form expressions for the loop filter coefficients in modulators using nonreturn-to-zero and return-to-zero digital-to-analog converters. Simulation results confirming the theory are given.
Chopping is a commonly used technique to eliminate flicker noise in amplifiers. We investigate the use of chopping in the input integrator of a continuous-time oversampling (AΣ) converter. Unlike an ...amplifier, the integrator in a continuous-time delta-sigma modulator is subject to out-of-band signals that are several orders of magnitude higher than the (desired) in-band component. This necessitates a careful analysis of frequency translation effects in a chopped integrator. This paper treats the chopped integrator as a linear periodically time-varying system, and exploits the adjoint (inter-reciprocal) network concept to simplify the analysis of aliasing effects in such an integrator. Simulation results that confirm the theory are given.
Single-bit continuous-time delta-sigma modulators (CTDSM) using FIR feedback DACs inherit the appealing aspects of both single-bit and multibit designs, without the disadvantage of either approaches. ...In this work, we give a method for stabilizing a CTDSM that uses an FIR feedback DAC. Further, we show that increasing the number of taps beyond a certain number (dependent on the architecture and oversampling ratio of the modulator) does not improve performance. The results of our analysis are incorporated in the design of a third-order audio CTDSM which achieves a peak A-weighted SNR of 102.3 dB (raw SNR of 98.9 dB) and a spurious-free dynamic range of 106 dB in a 24 kHz bandwidth, while consuming only 280 μW from a 1.8 V supply.
We apply the "assisted opamp technique" to the design of a 1 GS/s single-bit continuous-time ΔΣ modulator (CTDSM) that achieves 10 bit resolution in 15.625 MHz bandwidth. The enhanced linearity and ...speed of the first integrator of the modulator, necessitated by single-bit operation, are obtained in a power efficient manner using opamp assistance. However, timing-skew between the feedback and assistant DAC currents can be a potential problem at high speeds. We analyze and give intuition for the effects of timing mismatch in such CTDSMs, and show that opamp assistance is quite robust to timing errors. Measurement results from an implementation in a 0.13 μ m CMOS process show that the modulator achieves a dynamic range of 67 dB in 15.625 MHz bandwidth while consuming 4 mW.
We present the design principles and circuit details of a single-bit continuous-time delta-sigma ADC that achieves 13.3-bit resolution over a 20-MHz signal bandwidth. The modulator, which operates at ...a sampling rate of 2.56 GHz in a 65-nm CMOS process, uses a 2<inline-formula> <tex-math notation="LaTeX">\times </tex-math></inline-formula> time-interleaved ADC to address the problem of comparator metastability. A 4<inline-formula> <tex-math notation="LaTeX">\times </tex-math></inline-formula> time-interleaved virtual-ground-switched resistive FIR feedback DAC is used for low distortion and power-efficient operation. Interleaving artifacts caused by DAC-element mismatch are addressed by mixed-signal calibration, which is enabled by the DAC architecture. The decimator is implemented using poly-phase techniques. A prototype modulator, which operates with a 1.1-V supply, achieves 82.1-dB peak SNDR and THD of 98.6 dBc while consuming 11.3 mW. The resulting Schreier FoM is 174.1 dB. The decimator dissipates 13.5 mW.
Circuits that generate a current or voltage proportional to absolute temperature are referred to as PTAT generators. Such circuits form the core of bandgap voltage references. This work derives ...textbook PTAT generator circuits from first principles, and shows these ideas can be used to generate alternative circuits.
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