High-resolution continuous-time delta-sigma modulators use resistive feedback DACs for low-noise operation. Such DACs have conventionally been switched at the reference end. It turns out that ...reference-path resistance degrades the performance of these DACs. This problem can be addressed by the virtual-ground-switched resistor DAC. However, moving the switches to the virtual-ground-side degrades alias-rejection of the modulator. This brief analyzes the mechanism of degradation and develops a model to estimate alias rejection. Our theory is supported by simulations and measurements from a prototype modulator designed in a 180nm CMOS process. We then describe a way to address this problem, and demonstrate its efficacy using layout-extracted simulations.
Chopping is an efficient way of mitigating the effect of flicker noise in continuous-time delta-sigma modulators (CT<inline-formula> <tex-math notation="LaTeX">{\Delta \Sigma } ...</tex-math></inline-formula>Ms). Unfortunately, chopping causes the demodulation of shaped quantization noise into the signal band. Prior works have analyzed noise-folding effects in chopped integrators that use single-stage and two-stage feedforward-compensated OTAs. These works use restrictive assumptions, such as settling of the OTA internal nodes at the chopping instants, and an NRZ feedback DAC waveform. This paper gives a general model for aliasing of shaped noise in a chopped integrator that incorporates arbitrary OTAs, arbitrary DAC pulse-shapes, and incomplete settling. Using the theory of linear periodically time-varying (LPTV) systems, we derive a simple simulation test-bench that can be used to estimate the parameters of our model. Thanks to this, the effects on chopping on the performance of the modulator can be rapidly estimated without running long transient simulations. Simulation and experimental results that support our theory are given.
Element mismatch in the digital-to-analog converter (DAC) of a multibit ΔΣ data-converter greatly degrades the modulator's in-band performance. One approach to correct these errors is to use an ...offline calibration method, based on measuring the output of the modulator in response to an in-band sinusoid. The drawback of this method, however, is the necessity for a distortion-free input sine-wave excitation. We propose a technique that dispenses with the need for a distortion-free input, thereby paving the way for the generation of the input tone on-chip. Apart from being a useful tool for debugging designs, it is a potential candidate for foreground calibration. Experimental results from a multibit modulator test chip, designed in a 180nm CMOS technology, are given.
We present design techniques for single-bit continuous-time delta-sigma modulators that attain high resolution (>16 bits) over a bandwidth (BW) that is more than ten times the audio range. We ...introduce the zapped, virtual-ground-switched dual return-to-open DAC which is immune to ISI and other transition-dependent errors. FIR feedback facilitates chopping, improves clock-jitter sensitivity and the loop filter's linearity. We show that the compensation FIR DAC, which is typically bulky, can be implemented in an extremely power- and area-efficient manner in a single-bit modulator using a capacitive DAC and passive summation. Thanks to these techniques, the fabricated prototype achieves 103.2-/104.3-dB signal to noise and distortion ratio (SNDR)/signal to noise ratio (SNR) in a 250-kHz bandwidth while operating at 48 MS/s. Consuming 17.7 mW from a 1.8-V supply, the modulator occupies 1.1 mm 2 in a 180-nm CMOS process. The Schreier (SNDR) figure of merit (FoM) is 174.7 dB.
We present design considerations for CT<inline-formula> <tex-math notation="LaTeX">\!\Delta \!\Sigma </tex-math></inline-formula>Ms that attempt to achieve high resolution (16+ bits) over a wide ...bandwidth (>200 kHz), resulting in a low in-band noise spectral density. The main challenges in such designs are parasitic resistance in the reference path, inter-symbol interference (ISI) in the feedback-digital-to-analog converter (DAC) waveform, and flicker noise of the input operational transconductance amplifier (OTA). We introduce the virtual-ground-switched resistor DAC as a way to achieve low distortion by addressing parasitic resistance in the reference path and reducing the effects of ISI. Flicker noise is reduced by chopping the first stage of the input OTA. Chopping artifacts and clock jitter sensitivity are reduced by using a three-stage OTA and finite impulse response (FIR) feedback. These techniques are applied to the design of a 250 kHz bandwidth CT<inline-formula> <tex-math notation="LaTeX">\!\Delta \!\Sigma \text{M} </tex-math></inline-formula> targeting 108 dB signal-to-noise-and-distortion-ratio (SNDR) in a 180 nm CMOS process. The fabricated prototype, which operates at 32 MS/s, achieves 105.3/108.1 dB SNDR/signal-to-noise-ratio (SNR) and consumes 24 mW. The Schreier SNDR figure of merit (FoM) is 175.5 dB.
Chopping is an efficient way of mitigating the effect of flicker noise in continuous-time delta-sigma modulators (CTDSM). Unfortunately, chopping causes the demodulation of shaped quantization noise ...into the signal band. Prior works have analyzed noise-folding effects in chopped integrators that use single-stage and two-stage feedforward-compensated OTAs. These works use restrictive assumptions, like settling of the OTA internal nodes at the chopping instants, and an NRZ feedback DAC waveform. This work gives a general model for aliasing of shaped noise in a chopped integrator that incorporates arbitrary OTAs, arbitrary DAC pulse-shapes, and incomplete settling. Using the theory of linear periodically time-varying (LPTV) systems, we derive a simple simulation test-bench that can be used to estimate the parameters of our model. Thanks to this, the effects on chopping on the performance of the modulator can be rapidly estimated without running long transient simulations. Simulation and experimental results that support our theory are given.
CTDSMs with high resolution and bandwidth greater than 200kHz are needed in industrial, medical, and automotive applications. Such high performance demands very low noise and distortion. The noise ...and distortion have to be suppressed even further in advanced technologies due to the low voltage headroom. A major challenge of low noise and distortion design is the large area cost of DAC and loop filters. The main feedback RDAC occupies a large area in 1. 1st-order data weighted average (DWA) is used but has limited mismatch error suppression. There is also a kink in the SNDR plot of 1 at low input amplitudes due to tones caused by DWA. To reduce the area, 2, 3 use DWA for the MSB bits and mismatch error shaping (MES) for the LSB bits. MES enables the binary coded DAC to save the LSB DAC area. However, the overall DAC's mismatch-induced distortion is dominated by the MSB bits. Thus, the approach of 2, 3 yields limited performance benefits due to the relatively mild 1st-order mismatch error shaping obtained from the DWA operation on the MSB bits.
High-performance instrumentation and communications demand an ADC technology push to achieve both - an ultra-low NSD of -164dBFS/Hz and HD 3 /IM 3 <−80dBFS - over a BW >500MHz with sub-Watt power ...dissipation. 3 rd -order distortion matters since for modulated inputs it falls near the signal and limits EVM. Combined with ultra-low NSD, it ensures robustness to large interferers when detecting small signals. Pushing DT ADCs to such performance via impedance scaling imposes significant overhead in the driver and antialiasing filter (AAF). E.g. 1 would need to be ~25×-parallelized to reach the NSD (but would still violate HD 3 ), requiring a large ~27pF load to be driven at 900MHz BW with low NSD, HD 3 , and kickback. AAF design, too, is not easy due to tradeoffs between order, insertion loss, and group delay. CT ΔΣ ADCs are more system-friendly since their resistive input impedance (Z in ) and implicit antialiasing (AA) relax the driver and AAF. However, a single-loop CT ΔΣ ADC requires an OSR>16 to be energy efficient. For BW >500MHz, this translates to a very high f s and, consequently, high power dissipation.
Continuous-time delta-sigma (CT DSM) ADCs offer implicit antialiasing and a resistive input impedance. This allows a dramatic relaxation of the ADC's antialiasing filter requirement and a drastic ...simplification of its driver's design. This has proved transformative in the particular case of integrated narrowband direct conversion receivers (RXs) where, following the mixer, a simple T1A with a firstorder roll-off is sufficient to drive the ADC (Fig. 1). The ADC, however, must be easy to integrate, have no signal transfer function (STF) peaking, and satisfy the stringent requirements of >90dB SFDR with >80dB antialiasing and an NSD <-150dBFS/Hz over lMHz bandwidth with low power dissipation. The resistive feedback DAC (RDAC) has been critical to achieving a low-NSD CT DSM with low power. However, reference-switched RDACs (Fig. 2) suffer from higher sensitivity to reference impedance 1. The virtual-ground-switched RDACI is less sensitive to this, but sampling of the virtual ground node by the RDAC switches severely degrades the ADC's antialiasing; e.g., it is only 50dB in 1 2. Further, prior RDAC work relies on off-chip references 1 -4, a major limitation for an ADC that is part of a production-level integrated RX due to associated overheads such as extra 1/O pins and need for external decoupling.
We present a CT\Delta \Sigma M which uses a virtual-ground-switched resistor DAC to achieve low distortion by reducing the effects of inter-symbol interference (ISI), and parasitic resistance in the ...reference path. 1/ f noise is reduced by chopping the first stage of the input OTA. Chopping artifacts and clock jitter sensitivity are reduced by using a 3-stage OTA, and an 8-tap FIR feedback DAC. Fabricated in 180nm CMOS, the prototype modulator operates at 32MS/s and achieves 103.5/107.5dB SNDR/DR in a 250kHz bandwidth while consuming 24mW. The Schreier FoM is 173.7dB.
