The LHCb experiment has gone through a major upgrade for LHC Run 3 at CERN, scheduled to start in the middle of 2022. The entire readout system of the experiment has been replaced by Front-End and ...Back-End electronics that are able to record LHC events at the full LHC bunch crossing rate of 40 MHz. In order to maintain synchronicity across the full system, clock and control commands are originated from a single Readout Supervisor (SODIN) and distributed downstream through a Passive Optical Network (PON) infrastructure, reaching all Back-End cards of the readout system, via a two-level hierarchy and utilizing PON splitters. An FPGA firmware core, called LHCb-PON and based on the CERN TTC-PON, is instantiated on SODIN and all Back-End cards and provides the communication protocol while ensuring a stable distribution of control commands within the readout period of 25 ns as well as a clock signal with fixed and deterministic latency with a precision of a few hundreds of picoseconds. This is achieved by the firmware backbone that provides clock recovery and ensures the transmission of a control word downstream with fixed latency. Additionally, the LHCb-PON also provides monitoring functionalities over the upstream link, with less strict timing requirements, connecting multiple Back-End cards to the central SODIN. This is achieved by having each Back-End card send data upstream through a Time Division Multiplexing scheme. This paper describes the implementation, measurements and results from the usage of the system during the start-up of The LHC Run 3.
In 2019, the LHCb experiment at CERN will undergo a major upgrade where its detector electronics and the entire readout system will be replaced. The goal is to read-out all events at the full LHC ...frequency of 40 MHz, reaching a total data rate of ~40 Tb/s. In this context, a new timing, trigger and readout control system has been developed: its main tasks are to distribute centrally the clock, the timing information and to synchronize all elements in the readout system: from the very last Front-End ASIC to the building of events to be stored. The heart of the timing and readout control system is a VHDL firmware core that is now finalized and currently in use in test-benches and test-beams by the upgraded sub-detectors, for their initial commissioning phase. Such firmware core is able to generate all necessary processes to keep the synchronization of all readout elements with the LHC bunch crossing as well as it is able to generate asynchronous commands for calibration or test purposes. It is also able to accommodate for specific recipes to handle varying running conditions, by using a generic and fully configurable approach. In this paper, the philosophy and the implementation behind such firmware are described in details, posing particular emphasis to the real-time logical processes that were developed in order to satisfy the requirements of synchronization and readout control of the upgraded LHCb detector.
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