Ryanodine receptor (RyR) Ca
-release channels are essential for contraction in skeletal and cardiac muscle and are prime targets for modification of contraction in disorders that affect either the ...skeletal or heart musculature. We designed and synthesized a number of compounds with structures based on a naturally occurring peptide (A peptides) that modifies the activity of RyRs. In total, 34 compounds belonging to eight different classes were prepared. The compounds were screened for their ability to enhance Ca
release from isolated cardiac sarcoplasmic reticulum (SR) vesicles, with 25 displaying enhanced Ca
release. Competition studies with the parent peptides indicated that the synthetic compounds act at a competing site. The activity of the most effective of the compounds, BIT 180, was further explored using Ca
release from skeletal SR vesicles and contraction in intact skeletal muscle fibers. The compounds did not alter tension in intact fibers, indicating that (as expected) they are not membrane permeable, but importantly, that they are not toxic to the intact cells. Proof in principal that the compounds would be effective in intact muscle fibers if rendered membrane permeable was obtained with a structurally related membrane-permeable scorpion toxin (imperatoxin A), which was found to enhance contraction.
•We jointly exploit the sparsity of radar echoes in the fast-time domain and the sparsity of the RFI sources in the fast-frequency domain.•We introduce a one-bit weighted SPICE based framework to ...jointly mitigate the RFI sources and recover the radar echoes from the signed measurements of the one-bit UWB radar systems.•The one-bit weighted SPICE based framework improves the performance of RFI mitigation and echo recovery and reduces the computational cost if compared to the existing method.
Radio frequency interference (RFI) mitigation and radar echo recovery are critically important for the proper functioning of ultra-wideband (UWB) radar systems using one-bit sampling techniques. We recently introduced a technique for one-bit UWB radar, which first uses a majorization-minimization method for RFI parameter estimation followed by a sparse method for radar echo recovery. However, this technique suffers from high computational complexity due to the need to estimate the parameters of each RFI source separately and iteratively. In this paper, we present a computationally efficient joint RFI mitigation and radar echo recovery framework to greatly reduce the computational cost. Specifically, we exploit the sparsity of RFI in the fast-frequency domain and the sparsity of radar echoes in the fast-time domain to design a one-bit weighted SPICE (SParse Iterative Covariance-based Estimation) based framework for the joint RFI mitigation and radar echo recovery of one-bit UWB radar. Both simulated and experimental results are presented to show that the proposed one-bit weighted SPICE framework can not only reduce the computational cost but also outperform the existing approach for decoupled RFI mitigation and radar echo recovery of one-bit UWB radar.
Coded modulation (CM) is the combination of forward error correction (FEC) and multilevel constellations. Coherent optical communication systems result in a four-dimensional (4D) signal space, which ...naturally leads to 4D-CM transceivers. A practically attractive design paradigm is to use a bit-wise decoder, where the detection process is (suboptimally) separated into two steps: soft-decision demapping followed by binary decoding. In this paper, bit-wise decoders are studied from an information-theoretic viewpoint. 4D constellations with up to 4096 constellation points are considered. Metrics to predict the post-FEC bit-error rate (BER) of bit-wise decoders are analyzed. The mutual information is shown to fail at predicting the post-FEC BER of bit-wise decoders and the so-called generalized mutual information is shown to be a much more robust metric. For the suboptimal scheme under consideration, it is also shown that constellations that transmit and receive information in each polarization and quadrature independently (e.g., PM-QPSK, PM-16QAM, and PM-64QAM) outperform the best 4D constellations designed for uncoded transmission. Theoretical gains are as high as 4 dB, which are then validated via numerical simulations of low-density parity check codes.
Van der Waals (vdW) heterostructures with 2D materials have shown that atomically thin non‐volatile memories are advantageous in terms of integration, while offering high performance and excellent ...stability. The non‐volatile memory behavior of 2D materials has mainly been studied for single‐bit operation, and there is growing interest in expanding to multi‐bit operation to enhance the storage capacities of memory devices. However, the conditions or rules for generating the desired number of bits in 2D‐based multi‐bit memory remain to be identified. In this study, multiple bits are successfully created on non‐volatile memory based on vdW heterostructure floating‐gate memory (FGM) by systematically tuning the dimensions of the 2D materials. In particular, a fingerprint mechanism is established that links the bit number and dimensions of 2D crystals on vdW heterostructures. This approach could enable the precise generation of the desired number of bits in layered‐material‐based vdW FGMs.
Multiple bits are successfully created on non‐volatile memory based on vdW heterostructure floating‐gate memory (FGM) by systematically tuning the dimensions of the 2D materials. In particular, a fingerprint mechanism is established that links the bit number and dimensions of 2D crystals on vdW heterostructures. This approach could enable the precise generation of the desired number of bits in layered‐material‐based vdW FGMs.
This article proposes a general-purpose hybrid in-/near-memory compute SRAM (CRAM) that combines an 8T transposable bit cell with vector-based, bit-serial in-memory arithmetic to accommodate a wide ...range of bit-widths, from single to 32 or 64 bits, as well as a complete set of operation types, including integer and floating-point addition, multiplication, and division. This approach provides the flexibility and programmability necessary for evolving software algorithms ranging from neural networks to graph and signal processing. The proposed design was implemented in a small Internet of Things (IoT) processor in the 28-nm CMOS consisting of a Cortex-M0 CPU and 8 CRAM banks of 16 kB each (128 kB total). The system achieves 475-MHz operation at 1.1 V and, with all CRAMs active, produces 30 GOPS or 1.4 GFLOPS on 32-bit operands. It achieves an energy efficiency of 0.56 TOPS/W for 8-bit multiplication and 5.27 TOPS/W for 8-bit addition at 0.6 V and 114 MHz.
Experimental results on the effect of Bit wear on torque response Karasawa, Hirokazu; Ohno, Tetsuji; Miyazaki, Kuniyuki ...
International journal of rock mechanics and mining sciences (Oxford, England : 1997),
April 2016, 2016-04-00, 20160401, Volume:
84
Journal Article
Peer reviewed
Percussion bits, polycrystalline diamond compact (PDC) bits and roller cone bits are widely used in well drilling. The evaluation methods for downhole conditions, such as the wear condition of drill ...bits and the in situ rock strength, are important issues in improving the drilling efficiency and reducing the drilling cost. In this study, drilling tests were conducted in laboratory using the three types of drill bit and various types of rock. On the basis of the results, a close relation between the bit wear condition and bit torque was found for each bit.
•The bit torque and height loss of tips on a percussion bit are closely related.•The bit torque changes with the wear of the cutters on PDC core bits.•The bit torque is useful for evaluating the tooth wear of roller cone bits.
Probabilistic computing can solve complex combinatorial optimization problems more efficiently than conventional deterministic computing. A probabilistic bit (p‐bit) with an n‐p‐n bistable resistor ...(biristor) is demonstrated for probabilistic computing. It is fabricated on an 8‐inch wafer with complementary metal–oxide–semiconductor (CMOS) compatible technologies. Its stochastic behavior of threshold switching, which is based on the phenomenon of a single transistor latch, provides output with a Boltzmann distribution. The p‐bit is composed of a biristor, a serial resistor, and a comparator. The output probability of the biristor‐based p‐bits shows a sigmoidal relationship with the input voltage, showing typical p‐bit characteristics. Invertible Boolean logic operations with p‐bits are demonstrated, and weighted maximum Boolean satisfiability problems are solved with high energy efficiency and accuracy. The biristor‐based p‐bits with perfect CMOS compatibility show sufficient device stability, demonstrating the possibility of large‐scale integration with a p‐bit array for complex optimization solvers.
A probabilistic bit (p‐bit) with an n‐p‐n bistable resistor is demonstrated for probabilistic computing. It is fabricated on an 8‐inch wafer with complementary metal–oxide–semiconductor compatible technologies. Based on the stochastic behavior of a single transistor latch, invertible Boolean logic operations are demonstrated, and weighted maximum Boolean satisfiability problems are solved with high energy efficiency and accuracy.
Bit fusion Sharma, Hardik; Park, Jongse; Suda, Naveen ...
Proceedings of the 45th Annual International Symposium on Computer Architecture,
06/2018
Conference Proceeding
Hardware acceleration of Deep Neural Networks (DNNs) aims to tame their enormous compute intensity. Fully realizing the potential of acceleration in this domain requires understanding and leveraging ...algorithmic properties of DNNs. This paper builds upon the algorithmic insight that bitwidth of operations in DNNs can be reduced without compromising their classification accuracy. However, to prevent loss of accuracy, the bitwidth varies significantly across DNNs and it may even be adjusted for each layer individually. Thus, a fixed-bitwidth accelerator would either offer limited benefits to accommodate the worst-case bitwidth requirements, or inevitably lead to a degradation in final accuracy. To alleviate these deficiencies, this work introduces dynamic bit-level fusion/decomposition as a new dimension in the design of DNN accelerators. We explore this dimension by designing Bit Fusion, a bit-flexible accelerator, that constitutes an array of bit-level processing elements that dynamically fuse to match the bitwidth of individual DNN layers. This flexibility in the architecture enables minimizing the computation and the communication at the finest granularity possible with no loss in accuracy. We evaluate the benefits of Bit Fusion using eight real-world feed-forward and recurrent DNNs. The proposed microarchitecture is implemented in Verilog and synthesized in 45 nm technology. Using the synthesis results and cycle accurate simulation, we compare the benefits of Bit Fusion to two state-of-the-art DNN accelerators, Eyeriss 1 and Stripes 2. In the same area, frequency, and process technology, Bit Fusion offers 3.9X speedup and 5.1X energy savings over Eyeriss. Compared to Stripes, Bit Fusion provides 2.6X speedup and 3.9X energy reduction at 45 nm node when Bit Fusion area and frequency are set to those of Stripes. Scaling to GPU technology node of 16 nm, Bit Fusion almost matches the performance of a 250-Watt Titan Xp, which uses 8-bit vector instructions, while Bit Fusion merely consumes 895 milliwatts of power.
In this study, the authors introduce a new framework for 1-bit compressed synthetic aperture radar (SAR) imaging by using time-varying thresholding. They show how to recover sparse SAR images from ...noisy measurements which have been quantised to 1-bit with time-varying thresholds. In the conventional 1-bit compressive sensing (CS) SAR imaging methods, 1-bit quantisation is implemented by comparing the received signal to a zero threshold. This makes the information about the magnitude of the signal to be lost and exact signal recovery becomes impossible. One-bit quantisation with time-varying thresholds allows them to reconstruct the magnitude of the signal more accurately and an explicit unit-norm constraint is no longer required in the proposed optimisation formulation. Using the proposed approach, the authors formulate 1-bit CS SAR imaging reconstruction problem as an unconstrained optimisation problem where the objective function includes an $\ell _2$ℓ2 data-fidelity term and a non-smooth regularisation function. In order to solve this unconstrained optimisation problem, they use variable splitting and the alternating direction method of multipliers based approach which is computationally efficient and easy to implement. The results from experiments with synthetic and real SAR images validate the effectiveness of the proposed method named as BCST-SAR (binary CS with time-varying thresholds in SAR imaging).
In this study, reduced precision operations are investigated in order to improve the speed and energy efficiency of SNN implementation. Instead of using the 32-bit single-precision floating-point ...format, small floating-point format and fixed-point format are used to represent SNN parameters and to perform SNN operations. The analyses are performed on the training and inference of a leaky integrate-and-fire model-based SNN that is trained and used to classify the handwritten digits in MNIST database. The analysis results show that for SNN inference, the floating-point format with 4-bit exponent and 3-bit mantissa or the fixed-point format with 6-bit integer and 7-bit fraction can be used without any accuracy degradation. For training, a floating-point format with 5-bit exponent and 3-bit mantissa or a fixed-point format with 6-bit integer and 10-bit fraction can be used to obtain full accuracy. The proposed reduced precision formats can be used in SNN hardware accelerator design and the selection between floating-point and fixed-point can be determined by design requirements. A case study of SNN implementation on field-programmable gate array device is performed. With reduced precision numerical formats, memory footprint, computing speed, and resource utilisation are improved. As a result, the energy efficiency of SNN implementation is also improved.
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