This brief presents an 8-GHz Octa-phase Error Corrector (OEC) employing a digital delay-locked loop (DLL) with a coprime phase comparison scheme. To alleviate timing constraint during the phase comparison, clock phases spaced in coprime to 8 is utilized, enabling up to a 64-Gb/s link operation. In particular, this brief applies 3T/8 spaced clock rather than T/8. In addition, by employing a clock-divided 5-bit selection scheme, a high-speed 8:2 multiplexer (MUX) operates seamlessly without glitches. To minimize a mismatch and calibration -induced jitter, a single shared phase comparator and a finite-state machine (FSM) for tracking the minimum total delay are employed. The test chip has been fabricated in the 40-nm CMOS technology in an active area of 0.0814 mm 2 . The core phase calibration loop consumes 10.8 mW at 8 GHz at a 0.9-V supply achieving a maximum residue phase error of 0.95 ps.