Design of a low-cost integrated 0.25 /spl mu/m CMOS Bluetooth SOC in 16.5 mm/sup 2/ silicon area

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Design of a low-cost integrated 0.25 /spl mu/m CMOS Bluetooth SOC in 16.5 mm/sup 2/ silicon area

Cheah, J.; Ee-Hong Kwek; Eng Chuan Low; Chee Kwang Quek; Yong, C.; Enright, R.; Hirbawi, J.; Lee, A.; Hongyu Xie; Longyin Wei; Le Luong; Jianping Pan; Shih-Tsung Yang; Lau, W.F.A.; Wai-Lim Ngai

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315), 2002, Volume: 1

Conference Proceeding

A complete 0.25 /spl mu/m CMOS SOC Bluetooth solution adopts a two-die in a single MCM chip packaging approach with minimum product cost as the most important design goal while maintaining competitive power consumption and RF performance.

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