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Marcinkevich, K R; Lunkov, P V; Kirienko, D A; Putrolaynen, V V; Belyaev, M A; Yartsev, A V
IOP conference series. Materials Science and Engineering, 06/2021, Volume: 1155, Issue: 1Journal Article
Abstract The paper presents the results of the development of a package-on-package multichip microcircuit with three-dimensional integration of processor and memory dies. The stages of fabrication the upper part of the microcircuit with several memory dies, which are mounted by the wire bonding method, and the lower part of the microcircuit, on which the processor die is attached by the flip-chip method, are described. After the fabrication of the microcircuit by combining the upper and lower substrates, a multi-stage functional testing of the processor and memory dies is performed using a test board and software loaded into the microcircuit memory.
