For the full exploitation of the excellent timing properties of the Multigap Resistive Plate Chamber (MRPC), front-end electronics with special characteristics are needed. These are (a) differential ...input, to profit from the differential signal from the MRPC (b) a fast amplifier with less than 1ns peaking time and (c) input charge measurement by Time-Over-Threshold for slewing correction. An 8-channel amplifier and discriminator chip has been developed to match these requirements. This is the NINO ASIC, fabricated with 0.25μm CMOS technology. The power requirement at 40mW/channel is low. Results on the performance of the MRPCs using the NINO ASIC are presented. Typical time resolution σ of the MRPC system is in the 50ps range, with an efficiency of 99.9%.
An ultrafast front-end preamplifier-discriminator chip called NINO has been developed for use in the ALICE time-of-flight detector. The chip has eight channels. Each channel is designed with an ...amplifier with less than 1-ns peaking time, a discriminator with a minimum detection threshold of 10 fC and an output stage. The output pulse has minimum time jitter (less than 25 ps) on the front edge, and the pulsewidth is dependent of the input signal charge. Each channel consumes 27 mW, and the eight channels fit in a 2/spl times/4 mm/sup 2/ ASIC processed in IBM 0.25-/spl mu/m CMOS technology.
The ATLAS detector is a general purpose experiment designed to fully exploit the discovery potential of the Large Hadron Collider (LHC) at a nominal luminosity of 10
34
cm
−2
s
−1. It is expected ...that after several years of successful data-taking, the LHC physics program will be extended by increasing the peak luminosity by one order of magnitude. For ATLAS, an upgrade scenario will imply the complete replacement of the Inner Detector (ID), since the current tracker will not provide the required performance due to cumulated radiation damage and a dramatic increase in the detector occupancy.
In this paper, a proposal of a double-sided silicon micro-strip module for the short-strip region of the future ATLAS ID is presented. The expected thermal performance based upon detailed FEA simulations is discussed. First electrical results from a prototype version of the next generation readout front-end chips are also shown.
Low-power amplifier-discriminators based on a so-called NINO architecture have been developed with high time resolution for the readout of radiation detectors. Two different circuits were integrated ...in the NINO13 chip, processed in IBM 130 nm CMOS technology. The LCO version (Low Capacitance and consumption Optimization) was designed for potential use as front-end electronics in the Gigatracker of the NA62 experiment at CERN. It was developed as pixel readout for solid-state pixel detectors to permit minimum ionizing particle detection with less than 180 ps rms resolution per pixel on the output pulse, for power consumption below 300 muW per pixel. The HCO version (High Capacitance Optimization) was designed with 4 mW power consumption per channel to provide timing resolution below 20 ps rms on the output pulse, for charges above 10 fC. Results presented show the potential of the LCO and HCO circuits for the precise timing readout of solid-state detectors, vacuum tubes or gas detectors, for applications in high energy physics, bio-technologies or medical imaging.
DMILL bipolar transistors (npn) were exposed to 24 GeV protons and fast and thermal neutrons to fluences up to 6/spl middot/10/sup 14/ n/cm/sup 2/. Transistor common emitter current gain (/spl ...beta/=I/sub collector//I/sub base/) was measured after irradiations. It was found that /spl beta/ degradation scales as /spl Delta/(1//spl beta/)=k/sub T//spl middot//spl Phi//sub T/ where /spl Phi//sub T/ is the fluence of thermal neutrons and as /spl Delta/(1//spl beta/)=k/sub eq//spl middot//spl Phi//sub eq/, with /spl Phi//sub eq/ 1-MeV equivalent fluence, if transistors are irradiated with protons or fast neutrons. Large damage factor k/sub T//spl sim/3/spl middot/k/sub eq/ was measured. Thermal neutrons do not have sufficient energy to displace a Si atom. Their damage mechanism is, therefore, identified with /sup 10/B(n,/spl alpha/)/sup 7/Li reaction from which energetic /spl alpha/ and Li particles produce bulk damage in the base of the device. Boron is used as the base dopant in these transistors having also highly doped regions below base contacts. Irradiations with neutrons with energies distributed from thermal to fast show that gain degradation adds up as /spl Delta/(1//spl beta/)=k/sub T//spl middot//spl Phi//sub T/+k/sub eq//spl middot//spl Phi//sub eq/.
We present the design and performance of the ABCN-25 readout chip implemented in 0.25 ¿m CMOS technology. The front-end design has been optimized for the short, 2.5 cm, silicon strips foreseen in the ...upgrade of the ATLAS Inner Detector. The core of the readout architecture includes binary front-end, two levels of data buffering, data compression and data serializing circuitry, and is similar to the architecture of the ABCD3T chip used in the present ATLAS SCT detector. In order to ensure required radiation hardness the hardening by layout technique has been used and SEU detection and correction circuitry have been added. The design includes on-chip power management circuitry comprising two types of shunt regulators and a serial regulator. This circuitry makes the ABCN-25 chip compatible with recent developments in the area of power distribution systems for the inner trackers in the SuperLHC environment and in particular with serial powering of the detector modules. The chip has been fabricated in 0.25 ¿m CMOS technology and full functionality has been obtained. The critical design aspects and performance of the analog and digital circuits will be presented and discussed.
Two prototype chips for the analogue readout of silicon strip detectors in the ATLAS Semiconductor Tracker (SCT) have been designed and manufactured, in 32 channel and 128 channel versions, using the ...radiation hard BiCMOS DMILL process. The SCTA chip comprises three basic blocks: front-end amplifier, analogue pipeline and output multiplexer. The front-end circuit is a fast transresistance amplifier followed by an integrator, providing fast shaping with a peaking time of 25 ns, and an output buffer. The front end output values are sampled at 40 MHz rate and stored in a 112-cell deep analogue pipeline. The delay between the write pointer and trigger pointer is tunable between 2 /spl mu/s and 2.5 /spl mu/s. The chip has been tested successfully and subsequently irradiated up to 10 Mrad. Full functionality of all blocks of the chip has been achieved at a clock frequency of 40 MHz both before and after irradiation. Noise figures of ENC=720 e/sup -/+33 e/sup -//pF before irradiation and 840 e/sup -/+33 e/pF after irradiation have been obtained.
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