Recently, radio frequency identification (RFID) systems have gained popularity in manufacturing units, inventory, and logistics, as they represent an inexpensive and reliable solution for automatic ...identification. Moreover, RFID transponders are expected to become a key element in the ubiquitous computing scenario. Tags will likely be used to collect sensors data, enabling noninvasive environment monitoring. Low-cost passive UHF transponders are expected to play a major role in this context, due to extended read range capabilities. Within a passive tag, power harvested from the field irradiated by the reader during the communication should operate both digital control circuitry and potential sensing devices. Exploiting ultra-low power tag circuitry would provide sensing sections with higher energy, thus improving measurement performance. In this paper, the design of a novel circuit is presented, which implements the baseband processor of a UHF-RFID tag in compliance with the ISO 18000-6B protocol. Regardless of protocol selection issues, several power saving strategies are devised, both at the system and circuit levels, suitable for passive transponder implementation. Near-threshold operation has been exploited to attain ultra-low power consumption while keeping fair performance. A set of standard cells has been designed, suitable for the power-limited specific application. The proposed solution has been successfully checked by means of a physical implementation on CMOS 0.18 mum technology. Test chips have been characterized in terms of voltage and frequency operating range and power consumption figure has been extensively analyzed. Measurement results fully support the selected design approach: the baseband processor dissipates only 440 nW average power when operated at 800 kHz and 0.6 V. This extremely-low power consumption enables high-performance ubiquitous computing.
A three-dimensional (3-D) implementation of the lumped-element finite-difference time-domain (FDTD) algorithm has been carried out. To accomplish proper description of device dynamic responses, the ...code incorporates accurate models of lumped bipolar devices, including nonlinear capacitances associated with pn and Schottky junctions. The nonlinear system arising from discretized lumped-element equations is solved by means of an iterative Newton-Raphson algorithm, the convergence properties of which are sensitive to the value of the simulation time step. The computational efficiency of the algorithm (as well as its robustness) has significantly been enhanced by introducing an adaptive time-step algorithm, which dynamically adjusts the time-step itself to ensure convergence during the simulation. Several simulation examples are compared with conventional analysis techniques and demonstrate the algorithm reliability as well as its increased efficiency.
In this paper, the issue of numerical modeling of radiation-damaged silicon devices is discussed, with reference to radiation detectors employed in high-energy physics experiments. Since the actual ...physical picture is far too complex to be accounted for at a first-principle (i.e., defect kinetics) level and not yet fully understood, a hierarchical approach has been followed looking for a suitable approximation of macroscopic changes of the electrical behavior of silicon device induced by radiation damage. In particular, a three deep-level trapping mechanism is accounted for by means of Shockley-Read-Hall theory, whereas the shallow-level sensitivity on the radiation is considered by means of a donor-removal model.
This paper aims at exploring and validating the adoption of standard fabrication processes for the realization of CMOS active pixel sensors, for particle detection purposes. The goal is to implement ...a single-chip, complete radiation sensor system, including on a CMOS integrated circuit the sensitive devices, read-out and signal processing circuits. A prototype chip (RAPS01) based on these principles has been already fabricated, and a chip characterization has been carried out; in particular, the evaluation of the sensitivity of the sensor response on the actual operating conditions was estimated, as well as the response uniformity. Optimization and tailoring of the sensor structures for High Energy Physics applications are being evaluated in the design of the next generation chip (RAPS02). Basic features of the new chip includes digitally configurable readout and multi-mode access (i.e., either sparse of line-scan readout).
In this paper, we discuss some issues related to the design, implementation, and test of a CMOS active pixel sensor chip (RAPS01), developed in the framework of the radiation active pixel sensors ...(RAPS) INFN project. Two different basic pixel schemes have been proposed. The first one is based on a standard active pixel sensor (APS) architecture, while a second architecture, named weak inversion pixel sensor (WIPS) exploits a different circuitry which allows for "sparse" access mode and thus for speeding-up the readout phase. Chip fabrication has been completed and a preliminary test phase has been performed. A suitable test environment has been devised and test strategies have been planned. Preliminary test results, featuring a static and dynamic characterization of the basic sensitive elements are outlined. Future works are also outlined, aimed at the optimization of a second version of the chip, more effectively integrating smart circuitry.
In this paper, a simulator based on a global electromagnetic model is presented, suited for the analysis of HF integrated and hybrid electronic circuits. The model is based on the self-consistent ...solution of Maxwell's equation and of semiconductor transport equations, exploiting a generalized finite-difference time-domain (FDTD) scheme. The tool is, therefore, capable of accounting, on a distributed basis, for actual interactions between wave propagation and charge transport, anti is capable of providing a physically based picture of traveling-wave semiconductor devices. The implementation is such that more conventional algorithms (e.g. lumped-element FDTD or plain FDTD) can be regarded as a subset of the global scheme itself. This makes it possible to intermix different physical models, featuring different degrees of physical accuracy and computational efficiency, within the same simulation environment. Main features of such an environment are described by means of the simulation of a simple 76-GHz distributed switch.
Design and test of innovative CMOS pixel detectors Passeri, D.; Placidi, P.; Petasecca, M. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
12/2004, Letnik:
535, Številka:
1
Journal Article
Recenzirano
In this work, design, implementation and test phases of a radiation sensor based on active pixel architectures are discussed. Fully standard CMOS technology has been exploited, allowing for easier ...integration of signal-processing circuitry. Alternative circuit schemes have been considered; a novel architecture, called WIPS, is introduced, aimed at a more efficient sparse-access mode of the sensor array. A first prototype of the chip has been fabricated, in a
0.18
μ
m
CMOS technology. An automatic testing procedure has been devised, including design and fabrication of a suitable test board and of an optical bench. Preliminary results of the measurements are given, validating the overall approach and the operating principle of the WIPS architecture.
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