The superB silicon vertex tracker Rizzo, G.; Avanzini, C.; Batignani, G. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
05/2010, Letnik:
617, Številka:
1
Journal Article
Recenzirano
Odprti dostop
The SuperB asymmetric
e
+
–
e
-
collider has been designed to deliver a luminosity greater than
10
36
cm
-
2
s
-
1
with moderate beam currents. Comparing to current B-Factories, the reduced center of ...mass boost of the SuperB machine requires improved vertex resolution to allow precision measurements sensitive to New Physics. We present the conceptual design of the silicon vertex tracker (SVT) for the SuperB detector with the present status of the R&D on the different options under study for its innermost Layer0.
GigaFitter: Performance at CDF and perspective for future applications Amerio, S.; Annovi, A.; Basile, M. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
11/2010, Letnik:
623, Številka:
1
Journal Article
Recenzirano
The Silicon Vertex Trigger (SVT) at CDF is made of two pipelined processors: the Associative Memory finding low precision tracks and the Track Fitter refining the track quality with high-precision ...fits. We will describe the performance of a next generation track fitter, the GigaFitter, that performs more than a fit per nanosecond. It is going to be inserted parasitically in SVT to study its capabilities to improve data taking during the high luminosity CDF runs. This device is based on modern FPGA technology, rich of powerful DSP arrays, to reduce the track parameter reconstruction to few clock cycles and perform many fits in parallel. The goal of the design was to reduce significantly the processing time required for fitting and thus allow more time for the subsequent high resolution track-fitting. Preliminary results on the algorithm latency are presented. A future more power-full version of the GigaFitter intended for LHC experiments is also discussed.
In September 2008 the SLIM5 collaboration submitted a low material budget silicon demonstrator to test with 12
GeV/
c protons, at the PS-T9 test-beam at CERN. Two different detectors were placed as ...DUTs inside a high-resolution and fast-readout beam telescope. The first DUT was a high resistivity double sided silicon detector, with short strips (“striplets”) and with reduced thickness, at
45
∘
angle to the detector's edge, readout by the data-driven FSSR2 chip. The other one was a 4k-Pixel Matrix of Deep N Well MAPS, developed in a 130
nm CMOS Technology, providing digital sparsified readout. In the following, I present the striplets and also the beam telescope characteristics, with some details about the frontend readout (based on the FSSR2 chip) and some preliminary results of the data-analysis.
We report on further developments of our proposed design approach for a full in-pixel signal processing chain of deep N-well monolithic active pixel sensor, by exploiting the triple well option of a ...CMOS 130
nm process. Two different geometries of the collecting electrode (namely “Apsel 3
T
1
M
1” and “Apsel 3
T
1
M
2”) was implemented to compare their charge collection efficiency. The results of the characterization of the various versions of pixel matrices with a pion beam of 120
GeV/
c at the SPS H6 CERN facility will be presented. The performances of an “Apsel 3
T
1” chip irradiated with a dose up to 10
Mrad (Co
60) was also measured. Comparison will be presented among the irradiated and the new chip showing the impact of radiation damages on tracking efficiencies.
The Fast Track processor (FTK) has been proposed for high-quality track finding at very high rates (Level-1 output rates) for the LHC experiments. Fast, efficient and precise pattern recognition has ...been studied using a silicon 7-layer sub-detector, including a subset of the pixel and SCT layers. We tested the FTK algorithms using the ATLAS full simulation. We compare the FTK reconstruction quality with the tracking capability of the offline iPatRec algorithm. We show that similar resolutions and efficiencies are reached by FTK at a speed higher than iPatRec by orders of magnitude. With FTK full events are reconstructed at the Level-1 output rate. B o s rarr mu + mu - events are fufly simuiated together with background samples. We show that a low Level-2 rate is allowed by FTK, even using a singie 6 GeV Level-1 muon selection trigger. FTK provides the full-resolution track list ready for the Level-2 BB o s identification. All selection cuts performed by the Event Filter can be easily anticipated at Level-2. We present the B o s rarr mu + mu - efficiency gain and related Level-2 rates.
Interventional radiologists and staff members, during all their professional activities, are frequently exposed to protracted low doses of ionizing radiation. The authors present a novel approach to ...perform on line monitoring of the staff during interventional procedures by using a device based on a CMOS Active Pixel Sensor (APS). The sensor performance as an X-ray radiation detector has been evaluated with a dedicated experimental set-up and dosimetric observables have been assessed from the frames acquired by the sensor using a purposely designed algorithm. A data reduction strategy has also been implemented without significant loss of the performances. Finally a linear correlation with dosimetric measurements made using TLDs has been verified.
The Associative Memory (AM) system of the Fast TracKer (FTK) processor has been designed to perform pattern matching using as input the data from the silicon tracker in the ATLAS experiment. The AM ...is the primary component of the FTK system and is designed using ASIC technology (the AM chip) to execute pattern matching with a high degree of parallelism. The FTK system finds track candidates at low resolution that are seeds for a full resolution track fitting. The AM system implementation is named "Serial Link Processor" and is based on an extremely powerful network of 2 Gb/s serial links to sustain a huge traffic of data. This paper reports on the design of the Serial Link Processor consisting of two types of boards, the Little Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME motherboard which hosts four LAMB daughterboards. We also report on the performance of the prototypes (both hardware and firmware) produced and tested in the global FTK integration, an important milestone to be satisfied before the FTK production.
The high rate data acquisition system for the SLIM5 beam test Fabbri, L.; Bruschi, M.; Di Sipio, R. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
05/2010, Letnik:
617, Številka:
1
Journal Article
Recenzirano
In September 2008 the Slim5 collaboration submitted a low material budget silicon demonstrator to test with protons at the PS beam at CERN. The beam test setup was composed of a four double sided ...microstrip reference telescope and different detectors (DUTs) placed inside: a 4k-Pixel Matrix of Deep N Well MAPS, developed in a 130
nm CMOS Technology and a high resistivity double sided silicon detector, with short strips at
45
∘
angle to the detectors edge, read out by the FSSR2 chip. All the systems were self-triggered and read out by a fast DAQ system. In the poster the beam test setup as the data acquisition and the trigger system are explained and the data acquisition performances are shown.
The Silicon Vertex Trigger (SVT) is a processor developed at CDF experiment to perform online fast and precise track reconstruction. SVT is made of two pipelined processors, the Associative Memory, ...finding low precision tracks, and the Track Fitter, refining the track quality whith high precision fits. We will describe the architecture and the performances of a next generation track fitter, the GigaFitter, developed to reduce the degradation of the SVT efficiency due to the increasing instantaneous luminosity. The GigaFitter reduces the track parameter reconstruction to a few clock cycles and can perform many fits in parallel, thus allowing high resolution tracking at very high rate. The core of the GigaFitter is implemented in a modern Xilinx Virtex-5 FPGA chip, rich in powerful DSP arrays. The FPGA is housed on a mezzanine board which receives the data from a subset of the tracking detector and transfers the fitted tracks to a Pulsar motherboard for the final corrections. Instead of the current 12 boards, one per sector of the detector, the final system will be much more compact, consisting of a single GigaFitter Pulsar board equipped with four mezzanine cards receiving the data from the entire tracking detector. Moreover, the GigaFitter modular structure is adequate to scale for much better performances and is general enough to be easily adapted to future High Energy Physics (HEP) experiments and applications outside HEP.
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