As firms search to maximise value through the effective management of their various business activities, it is increasingly important to identify and understand the key factors that can significantly ...impact on the performance of the supply chain. The Supply Chain Operations Reference (SCOR) model enables to identify four distinct processes (plan, source, make and deliver) that constitute a supply chain. If many researchers have studied the last three processes (source, make and deliver), the relationship between the determinants of the planning process and supply chain performance has not been sufficiently explored. This paper therefore aims to identify and analyse the determinants of a distributed planning process that impact on the performance of a supply chain, including both financial and non-financial elements. It proposes a conceptual framework and a simulation model that can be used to improve the performance of a supply chain in terms of efficiency, flexibility, effectiveness and responsiveness.
This paper is to propose a generic analytic model to plan activities performed by common resources shared between different order makers. Considering the problem in a distributed and collaborative ...decision making context, a negotiation-based approach is proposed and systematized to express information exchanged between order makers and convergence criteria needed to rapidly calculate relevant planning solutions
L'Afrique face au développement durable Alexandre, Frédéric; Almoustapha, Oumarou; Amadou, Garba ...
VertigO : la revue électronique en sciences de l'environnement,
09/2006
Journal Article
The LHCb experiment is currently being installed at the Large Hadron Collider at CERN (Geneva, Switzerland). In order to reduce the amount of data storage for offline analysis, a trigger system is ...required. The Level-0 Decision Unit (LODU) is the central part of the first trigger level. It is a full custom 16 layers board using advanced FPGAs in BGA package. The LODU receives information from the Level-0 sub-triggers (432 bits @ 80 MHz) which transmit the data via high speed optical links running at 1.6 Gb/s. The processing is implemented using a 40 MHz synchronous pipelined architecture. It performs a simple physical algorithm to compute at 40 MHz the Level-0 trigger decision in order to reduce the data flow down to 1 MHz for the next trigger level. The internal design of the processing FPGA is mainly composed by a Partial Data Processing (PDP) and a Trigger Definition Unit (TDU). The aim of the PDP is to adjust the clock phase, perform the time alignment, prepare the data for the TDU and monitor the data processing. The TDU is flexible and allows to fully re-configure all the trigger conditions without any re-programming the FPGAs through the Experiment Control System (ECS).
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