The memristor-based convolutional neural network (CNN) gives full play to the advantages of memristive devices, such as low power consumption, high integration density, and strong network recognition ...capability. Consequently, it is very suitable for building a wearable embedded application system and has broad application prospects in image classification, speech recognition, and other fields. However, limited by the manufacturing process of memristive devices, high-precision weight devices are currently difficult to be applied in large-scale. In the same time, high-precision neuron activation function also further increases the complexity of network hardware implementation. In response to this, this paper proposes a configurable full-binary convolutional neural network (CFB-CNN) architecture, whose inputs, weights, and neurons are all binary values. The neurons are proportionally configured to two modes for different non-ideal situations. The architecture performance is verified based on the MNIST data set, and the influence of device yield and resistance fluctuations under different neuron configurations on network performance is also analyzed. The results show that the recognition accuracy of the 2-layer network is about 98.2%. When the yield rate is about 64% and the hidden neuron mode is configured as -1 and +1, namely ±1 MD, the CFB-CNN architecture achieves about 91.28% recognition accuracy. Whereas the resistance variation is about 26% and the hidden neuron mode configuration is 0 and 1, namely 01 MD, the CFB-CNN architecture gains about 93.43% recognition accuracy. Furthermore, memristors have been demonstrated as one of the most promising devices in neuromorphic computing for its synaptic plasticity. Therefore, the CFB-CNN architecture based on memristor is SNN-compatible, which is verified using the number of pulses to encode pixel values in this paper.
The memristive stateful logic can realize the memory and computation, thus effectively avoid the huge time and energy overhead caused by data moving between memory and computation units. However, the ...memristive stateful logic still faces the reliability challenges caused by the variability of memristor, which prevents it from practical applications. A reliability reinforcement method with low overhead in delay, area and peripheral circuits is thus needed to be studied urgently. This paper proposes a novel method of reliability reinforcement based on logic gates' margin. By optimizing circuit structure and driving voltage configuration, the margin of logic gates is improved to tolerant memristors' variability to the maximum extent, and thus reinforces logic gates' reliability. Simulations demonstrate that the proposed method can improve the allowed threshold variability range by 42% and 92% for 2‐input NAND gate and 2‐input OR gate, respectively. Benchmark with other methods shows that the proposed margin‐based reinforcement method achieves almost the same reliability reinforcement effect, but the overhead in area and peripheral circuit is greatly reduced.
In this paper, a novel method of reliability reinforcement based on logic gates' margin is proposed. By optimizing circuit structure and driving voltage configuration, the margin of logic gates is improved to tolerant memristors' variability to the maximum extent, and thus reinforce logic gates' reliability.
Mismatches between sub-channels limit the dynamic performance of time-interleaved analog-to-digital converters (TI-ADCs). This paper proposes a correlation-based method of calibration for timing ...mismatches in M-channel TI-ADCs by using the cross-correlation between sub-channels of the output signals to estimate the temporal deviations. The output signal is calibrated by reducing the arbitrary order distortion, which is approximated by multiplying the distortions with the estimated coefficients of mismatch. Furthermore, a reconfigurable strategy composed of stages of arbitrary calibration is proposed to achieve suitable stages with the requisite dynamic performance. Finally, the calibration performance of the proposed method is verified through simulations that use different input signals and strengths of mismatch.
The vector neural network (VNN) based on memristor has tremendous potential in applications such as electronic reconnaissance, medical diagnosis, and speech processing. However, the VNNs that ...encompass a huge amount of multiply-accumulate (MAC) operations often acquire network weights through massive numerical calculations with high precision, which results in a heavy consumption of energy and computing resource. Nevertheless, the resistance states of existing memristive devices can hardly meet the high-precision regulation requirements that restricts the application of VNN. We propose a binary memristor based vector-type back propagation (BMVTBP) architecture that integrates the advantages of low-precision memristive devices and VNN. The core function of this architecture is to realize the low-precision weights of three states by employing binarized memristive synapses, and further construct the positive and negative synaptic arrays to implement the MAC operations of interval data. Simulations verify the identification performance of the BMVTBP architecture on the emitter library. The ensuing results demonstrate that the identification rates exceed 96% and 87% for the interval-value and scalar-value noisy emitter samples, respectively, with an architecture requirement of only 1920 memristive devices and an energy consumption of about 2.43e-10 J.
To improve the user experience, an increasing number of mobile applications offload their computing tasks to servers with powerful computing capabilities. The fog radio access network (F-RAN) ...incorporates the concept of "fog computing" into the access network architecture, endowing an edge network with computing, storage, communication and control functions. In this paper, we consider a multiple fog access point (F-AP) and a multiuser F-RAN, where each user generates two different tasks: communication and computation. To satisfy the diverse quality of service requirements of different users, we jointly optimize the spectrum access, computation offloading and radio resource allocation. The problem is modeled as a mixed integer nonlinear programming problem, which is difficult to solve. In view of this, we propose a genetic algorithm based on convex optimization, i.e., the genetic convex optimization algorithm (GCOA), which divides the mixed integer nonlinear programming problem into two parts, i.e., optimization and convex optimization, to solve it in polynomial time. Simulation results are provided to verify the effectiveness of the algorithm.
To cope with the problem of emitter identification caused by the radar words＇ uncertainty of measured multi-function radar emitters, this paper proposes a new identification method based on ...stochastic syntax-directed translation schema（SSDTS）. This method, which is deduced from the syntactic modeling of multi-function radars, considers the probabilities of radar phrases appearance in different radar modes as well as the probabilities of radar word errors occurrence in different radar phrases. It concludes that the proposed method can not only correct the defective radar words by using the stochastic translation schema, but also identify the real radar phrases and working modes of measured emitters concurrently. Furthermore, a number of simulations are presented to demonstrate the identification capability and adaptability of the SSDTS algorithm.The results show that even under the condition of the defective radar words distorted by noise,the proposed algorithm can infer the phrases, work modes and types of measured emitters correctly.
In order to enhance the effective resolution of time-interleaved analog-to-digital converters (TI-ADCs), both linear and nonlinear channel mismatches should be carefully calibrated. This paper ...concentrates on a bandwidth-efficient background calibration method for nonlinear errors in
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-channel TI-ADCs. It utilizes the least-mean square algorithm as well as a certain degree of oversampling to achieve adaptive mismatch tracking. The calibration performance and computational complexity are investigated and evaluated through behavioral-level simulations. Furthermore, a calibration strategy for narrow-band input signals is proposed and verified as an improvement of the basic calibration structure for such signals.
With the development of high-speed sampling and real-time signal processing technologies, the power consumption for implementing large-point FFT operations is drastically increasing in application ...systems. This paper presents an FFT preprocessing algorithm based on a multi-channel analysis filter bank, which is implemented by an efficient multi-phase parallel structure. The operating frequency is reduced to
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for each constituent channel, while the spectrum width and the resolution are maintained. Meanwhile, the valid frequency point can be correctly identified and the resulting error is controlled below -30dB. Compared with the two-dimensional FFT algorithm, the power consumption accelerating factor can reach 2.4~4 by utilizing 4-channel analysis filter bank.
Abstract
As one of the most classic reinforcement learning, Q_learning has a very wide range of applications in the control filed of robot. Path planning which is the center of robot control has high ...computation speed requirements for algorithms, so we need to accelerate by hardware while planning path using Q_learning. In this paper, a hardware accelerator architecture based on FPGA is implemented to accelerate Q_learning while used in path planning. And we evaluate our design on Artix-7 DDR3 board, leading to less FPGA resource consumption and swifter computation speed. Comparing to Q_learning which implemented based on CPU, the speed has improved approximately 519 times, achieving the purpose of accelerating the Q_learning algorithm.
Abstract This paper presents a dynamic comparator that achieves precise comparison across the entire full-scale range. The comparator, an essential component module in analog-to-digital converters ...(ADCs), is influenced by its input signal range, speed, and offset voltage, all of which impact the ADC’s performance. In the proposed comparator, a pre-amplification stage using PMOS as the input is incorporated alongside the comparator utilizing NMOS as the input, creating a complementary structure. This design ensures that at least one pre-amplification stage operates effectively, thereby maintaining the accuracy of the comparator as the input signal varies across the entire full-scale voltage range (0 to VDD). Through sound circuit design, the proposed comparator effectively avoids introducing additional distortion and noise. The performance of the comparator is verified under the 180 nm process. The comparator achieves accurate comparison across the entire full-scale range, with a standard deviation σ of the input offset voltage of 6 mV, noise of 450 uV, and a layout area of 467.36 um 2 . Simulation results demonstrate that the comparator exhibits excellent performance, providing stability assurance for the ADC and extending the ADC’s input signal range.
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