We present the design and performance of the ABCN-25 readout chip implemented in 0.25 ¿m CMOS technology. The front-end design has been optimized for the short, 2.5 cm, silicon strips foreseen in the ...upgrade of the ATLAS Inner Detector. The core of the readout architecture includes binary front-end, two levels of data buffering, data compression and data serializing circuitry, and is similar to the architecture of the ABCD3T chip used in the present ATLAS SCT detector. In order to ensure required radiation hardness the hardening by layout technique has been used and SEU detection and correction circuitry have been added. The design includes on-chip power management circuitry comprising two types of shunt regulators and a serial regulator. This circuitry makes the ABCN-25 chip compatible with recent developments in the area of power distribution systems for the inner trackers in the SuperLHC environment and in particular with serial powering of the detector modules. The chip has been fabricated in 0.25 ¿m CMOS technology and full functionality has been obtained. The critical design aspects and performance of the analog and digital circuits will be presented and discussed.
The ASDBLR application-specific integrated circuit (ASIC) provides eight channels of low-noise low-power high-rate on-detector readout suitable for the ATLAS transition radiation tracker (TRT) at the ...large hadron collider. The TRT's unprecedented wire chamber readout requirements of a maximum hit rate per wire of 20 MHz and double-pulse resolution of /spl sim/25 ns with position resolution of better than 150 /spl mu/m in a high radiation environment have been addressed in the design of the ASDBLR. A carefully tuned ion tail cancellation stage followed by an output sensing baseline restorer implemented in differential structures provides robust signal-processing combination compatible with the realities of ASIC design. Two comparators track the output of the signal-processing stage to provide tracking information from charged particles and evidence of higher energy transition radiation photons; their outputs are summed as current steps to form a differential ternary output. The ten-year total dose requirement for neutrons of 10/sup 14/ n/cm/sup 2/ and 1.5 MRad of ionizing radiation led to the implementation of this design in the radiation hardened DMILL process.
A 16-channel digital time-measurement readout chip (DTMROC) has been fabricated in TEMIC corporations 0.8-/spl mu/m DMnL BI-CMOS SOI radiation-hard process for the Large Hadron Collider's (LHC) ...Transition Radiation Tracker (ATLAS/TRT) at CERN, the chip receives discriminated straw-drift-tube signals from bipolar amplifier-shaper-discriminator chips (ASDBLR), measures the arrival time in 3.125-ns increments (/spl plusmn/1 ns), and stores the data in a pipeline for 3.3 /spl mu/s. A trigger signal (L1A) causes the data to be tagged with a time stamp and stored for readout. Up to 13 events may be stored in an on-chip buffer while data is being clocked out in a 40 MHz serial stream. The chip has been designed to function after exposure to 1/spl times/10/sup 14/ protons/cm/sup 2/ and 1.0 Mrad total dose. System beam-tests have demonstrated measurement of track positions with a resolution of 165 /spl mu/m and high efficiency at rates up to 18 MHz.
The ATLAS experiment is preparing for the planned luminosity upgrade of the LHC (the super-luminous LHC or sLHC) with a programme of development for tracking able to withstand an order of greater ...magnitude radiation fluence and much greater hit occupancy rates than the current detector. This has led to the concept of an all-silicon tracker with an enhanced performance pixel-based inner region and short-strips for much of the higher radii. Both sub-systems employ many common technologies, including the proposed “stave” concept for integrated cooling and support. For the short-strip region, use of this integrated stave concept requires single-sided modules mounted on either side of a thin central lightweight support.
Each sensor is divided into four rows of 23.82
mm length strips; within each row, there are 1280 strips of 74.5μm pitch. Well over a hundred prototype sensors are being delivered by Hamamatsu Photonics (HPK) to Japan, Europe and the US.
We present results of the first 20 chip ABCN25 ASIC hybrids for these sensors, results of the first prototype 5120 strip module built with 40 ABCN25 read-out ASICs, and the status of the hybrids and modules being developed for the ATLAS tracker upgrade stave programme.
For the medium-energy proton polarimeter mounted at the focal-plane of the Big-Bite Spectrometer at Kernfysisch Versneller Instituut Groningen, a new wire-chamber readout has been developed. The ...charge-sensitive preamplifier is based on the ASD-8 B chip which has an input impedance of 115 /spl Omega/. This low impedance and the short integration time of 6 ns at a usable sensitivity of 5 fC allow high readout rates and low gas amplifications. This front-end circuit is mounted on all four multi-wire proportional chambers and on two vertical-drift chambers with 3872 wires in total. Measurements have been made using sources and intermediate energy protons. Special attention was given to determine the time-over-threshold properties of the circuit. The time-over-threshold capabilities of the readout system extend future applications to particle discrimination, or, in connection with other detector types, to energy-resolving readout. The operational performance of the readout system is presented.
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