The performance of Si0.75Ge0.25-channel Formula Omitted-type nanosheet (NS) devices with a gate length of 14 nm and a sheet width of 12 nm is investigated by Monte Carlo (MC) device simulation. It is ...found that the stress in the Si–Ge channel can eliminate the performance imbalance with Formula Omitted-type NSs arising from the (001) surface in the absence of stress. The performance is the same as the theoretical performance of Si-channel (cSi) Formula Omitted-type NSs with Si0.5Ge0.5 source/drain (S/D) pockets under the ideal assumption that no stress relaxation, e.g., due to grain boundaries from merging epitaxial growth occurs for the cSi devices. It is shown that the performance levels can be related to stress-induced quasi-ballistic velocity overshoot and the impact of alloy scattering. This is not captured by standard drift–diffusion (DD) simulation where a smaller saturation velocity predicts a performance degradation for Si–Ge channel devices.
Analytic doping profiles and contact resistivities are adjusted to reproduce measured transfer characteristics of state-of-the-art n-type and p-type FinFETs by Monte Carlo device simulation. The ...results are used to compare the performance of nanosheets (NSs) and FinFETs at advanced-node device dimensions. It is found that the ON-current normalized by the effective gate width reduces for a higher number of sheets due to a higher access resistance of the lower-lying sheets. In order to reach the same absolute current level of FinFETs with a fin height of 55 nm, more than two sheets for n-type and about four sheets for the p-type NSs with a NS width of 16 nm are needed, respectively. This technology computer-aided design (TCAD) approach can serve as input for design-technology cooptimization (DTCO) of advanced devices.
In order to outperform current uniaxial compressively strained Silicon channel pMOSFET technology (with embedded SiGe source/drain), switching to strained Ge channel is mandatory. GeSn materials, ...having larger lattice parameter than Ge, are proposed in this article as embedded source/drain stressors for Ge channels. Our simulation results indicate that a minimum of 5% Sn is required in the GeSn source/drain to build a competitive strained Ge pMOSFETs with respect to strained Si channels. Therefore the compatibility of GeSn (with 2–8% Sn) materials with source/drain engineering processes (B implantation and activation and NiGeSn formation) has been studied. A low thermal budget has been determined for those processes on GeSn alloys: temperatures must be lower than 600
°C for B activation and lower than 450
°C for NiGeSn formation.
This paper reports on 45-nm fin pitch strained p-type Ge gate-all-around devices fabricated on 300-mm SiGe strain-relaxed-buffers (SRB). By improving the process integration flow, excellent ...electrical performance is demonstrated: the <inline-formula> <tex-math notation="LaTeX">Q </tex-math></inline-formula> factor is increased to 25 as compared to our previous work, <inline-formula> <tex-math notation="LaTeX">I_{ \mathrm{\scriptscriptstyle ON}} = \textsf {500}~\mu \text{A}/ \mu \text{m} </tex-math></inline-formula> at <inline-formula> <tex-math notation="LaTeX">I_{ \mathrm{\scriptscriptstyle OFF}} = \textsf {100} </tex-math></inline-formula> nA/<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> is achieved, approaching the best published results on Ge finFETs. Good negative-bias temperature instability reliability is also maintained, thanks to the use of Si-cap passivation. The process flow developed for the fabrication of the single Ge nanowire (NW) is adapted and vertically stacked strained Ge NWs featuring 8-nm channel diameter are successfully demonstrated. A systematic analysis of the strain evolution is conducted on both single and double Ge NWs after the most challenging steps of the process integration flow: 1.7-GPa uniaxial-stress is demonstrated along the Ge wire, which originates from the lattice mismatch between the Ge source/drain and the Si 0.3 Ge 0.7 SRB.
Strained Ge p-channel gate-all-around (GAA) devices with Si-passivation are demonstrated on high-density 45-nm active pitch starting from 300-mm SiGe strain relaxed buffer wafers. While single ...horizontal Ge nanowire (NW) devices are demonstrated, the process flow described in this paper can be adjusted to make vertically stacked horizontal Ge NWs to increase the drive per footprint. The demonstrated short-channel devices have round Ge NWs with 9-nm diameter and are the Ge GAA devices with the smallest channel and gate dimensions (L G = 40 nm) published to date. Electrostatics and off-state leakage are maintained down to the shortest gate lengths studied, showing drain-induced barrier lowering of 30 mV/V and sub20 nA/μm I off at V DD = -0.5 V and L G = 40 nm. The short-channel device subthreshold slope SS and performance can be further improved by use of high-pressure annealing in hydrogen, yielding the best SSLIN and SSSAT of 71 and 76 mV/dec reported so far for any L G = 40-nm Ge pMOS channel device.
The performance of n-type silicon nanosheets, nanowires, and FinFETs is benchmarked by Monte Carlo (MC) device simulation. Measurements of nanowire transfer characteristics are provided to validate ...the MC model supplemented by a corresponding comparison for nanosheets with literature data. At an OFF-current per effective gate width of 10 nA/<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math> </inline-formula>, the ON-currents of nanowires, FinFETs, and nanosheets are 500, 545, and 570 <inline-formula> <tex-math notation="LaTeX">\mu \text{A}/\mu \text{m} </tex-math> </inline-formula>, respectively. A major reason for this inferior nanowire performance is found to be the stronger impact of surface roughness scattering in nanowires due to a higher surface-to-volume ratio. However, the nanowires’ performance disadvantage is reduced for shorter gate lengths due to their better electrostatic control and reduced impact of surface roughness upon scaling.
This paper presents an analysis of junction leakage in heavily doped p+/n germanium junctions, targeted for short-channel transistor fabrication. There exists an optimal p+/n junction condition, with ...a doping concentration of 1 times 10 17 -5 times 10 17 cm -3 , where the area-leakage-current density is minimal. Use of a halo-implant condition optimized for our 125-nm gate-length pMOS devices shows less than one decade higher area leakage than the optimal p+/n junction. For even higher doping levels, the leakage density increases strongly. Therefore, careful optimization of p+/n junctions is needed for decananometer germanium transistors. The junction leakage shows good agreement with electrical simulations, although for some implant conditions, more adequate implant models are required. Finally, it is shown that the area-junction static-power consumption for the best junctions remains below the power-density specifications for high-performance applications.
Ge pMOSFETs with HfO 2 gate dielectric and gate lengths down to 125 nm are fabricated in a Si-like process. Long-channel hole mobilities exceed the universal curve for Si by more than 2.5 times for ...vertical effective fields as large as 1 MV/cm. The mobility enhancement is found to be relevant at submicron gate lengths, and a drive current of 1034 muA/mum is achieved for L=125 nm at V G -V T =V D =-1.5 V. The introduction of halo implants allows significantly improved control of short-channel effects, with approximately three orders of magnitude reduction in source junction off-current. V T rolloff and drain-induced barrier lowering are reduced from 207 mV and 230 mV/V to 36 mV and 54 mV/V, respectively, for the highest n-well dose investigated. Four key logic benchmarking metrics are used to demonstrate that Ge is able to outperform Si down to the shortest investigated gate length, with an almost twofold improvement in intrinsic gate delay. I ON =722 muA/mum is demonstrated for I OFF =11 nA/mum at a power supply voltage of -1.5 V, when evaluating from the source.
We report on vertically stacked nanosheet (NS) FETs, focusing on the combined inner spacers and source/drain (S/D) epitaxial growth modules sequence, a key integration flow differentiator as compared ...to finFETs, addressing the impact and control of parasitics and channel strain engineering. The use of both wafer sides for device connection, via nTSVs landing on buried power rails (BPR) after extreme wafer thinning, is also discussed. This configuration is shown to be advantageous for obtaining reduced IR drop values and for, overall, enabling enhanced performance and additional area scaling. It also has the potential to further expand such as to include extra options, together with novel devices/circuits and for various applications.
In this work, we will give an overview of the innovation in materials and new device concepts that will be needed to continue Moore's law to the sub-10 nm technology nodes. To meet the power and ...performance requirements high mobility materials in combination with new device concepts like tunnel FETs and gate-all-around devices will need to be introduced. As the density is further increased and it becomes increasingly difficult to put contacts, spacers and gate in the available gate pitch, disruptive integration schemes such as vertical transistors and monolithic 3D integration might lead the way to the ultimate scaling of CMOS.
