The ALICE Zero Degree Calorimeters (ZDC) provide information about event geometry in heavy-ion collisions through the detection of spectator nucleons and allow to estimate the delivered luminosity. ...They are also very useful in p–A collisions, allowing an unbiased estimation of collision centrality. The Run 3 operating conditions will involve a tenfold increase in instantaneous luminosity in heavy-ion collisions, with event rates that, taking into account the different processes, could reach 5 MHz in the ZDCs. The challenges posed by this demanding environment lead to a redesign of the readout system and to the transition to a continuous acquisition. The new system is based on 12 bit, 1 Gsps FMC digitizers that will continuously sample the 26 ZDC channels. Triggering, pedestal estimation and luminosity measurements will be performed on FPGA directly connected to the front-end. The new readout system and the performances foreseen in Run 3 are presented.
In order to cope with the increased luminosity that the European Organization for Nuclear Research large hadron collider accelerator will provide after Long Shutdown 2 (2019- 2020), the a large ion ...collider experiment (ALICE) Time-Of-Flight (TOF) readout board data readout module is currently being redesigned. As a first step toward the final design, a test board hosting a Microsemi Igloo2 field-programmable gate array (FPGA), the radiation-hard Application-Specified Integrated Circuit (ASIC) gigabit transceiver ASIC (GBTX), and the optical transceiver versatile link transceiver (VTRX) has been designed and extensively tested. The basic idea is to use the GBTX ASIC for performing data transmission, trigger distribution, and clock forwarding toward the front-end electronics. Slow control links are implemented via an on-board advanced risc machine processor Ethernet link and via a 1.25-Gbps optical fiber using the Igloo2 FPGA internal serializer/deserializer. The board is going to work in a moderately hostile environment, having to face a total dose of 0.13 krads in ten years and a flux of 0.26 kHz/cm 2 of hadrons with energy above 20 MeV. The test board has extensively been tested with a special attention dedicated to the Igloo2-GBTX-VTRX devices. An upper bound estimation of the optical link bit error rate lower than 10 -14 is given, together with a measurement of the jitter of the GBTX output clock (around 55.3 ps peak-to-peak value), since this is a very crucial parameter for the TOF detector. The performances obtained by connecting the test board to a computer using the standard ALICE data acquisition board (named C-RORC) are also reported.
In this paper, different Silicon PhotoMultiplier (SiPM) sensors have been tested with charged particles to characterize the Cherenkov light produced in the sensor protection layer. A careful position ...scan of the SiPM response has been performed with different prototypes, confirming the large number of firing cells and proving almost full efficiency, with the SiPM filling factor essentially negligible. This study also allowed us to study the time resolution of such devices as a function of the number of firing cells, reaching values below 20 ps. These measurements provide significant insight into the capabilities of SiPM sensors in direct detection of charged particles and their potential for several applications.
The higher luminosity that is expected for the LHC after future upgrades will require better performance by the data acquisition system, especially in terms of throughput. In particular, during the ...first shutdown of the LHC collider in 2013/14, the ATLAS Pixel Detector will be equipped with a fourth layer – the Insertable B-Layer or IBL – located at a radius smaller than the present three layers. Consequently, a new front end ASIC (FE-I4) was designed as well as a new off-detector chain. The latter is composed mainly of two 9U-VME cards called the Back-Of-Crate (BOC) and Read-Out Driver (ROD). The ROD is used for data and event formatting and for configuration and control of the overall read-out electronics. After some prototyping samples were completed, a pre-production batch of 5 ROD cards was delivered with the final layout. Actual production of another 15 ROD cards is ongoing in Fall 2013, and commissioning is scheduled in 2014. Altogether 14 cards are necessary for the 14 staves of the IBL detector, one additional card is required by the Diamond Beam Monitor (DBM), and additional spare ROD cards will be produced for a total of 20 boards. This paper describes some integration tests that were performed and our plan to test the production of the ROD cards. Slices of the IBL read-out chain have been instrumented, and ROD performance is verified on a test bench mimicking a small-sized final setup. This contribution will report also one view on the possible adoption of the IBL ROD for ATLAS Pixel Detector Layer 2 (firstly) and, possibly, in the future, for Layer 1.
Recently the ATLAS Pixel Detector at CERN has been upgraded by inserting an additional layer of pixels, the Insertable B-Layer (IBL). In addition, the off-detector readout electronics of the other ...layers that composed the Pixel Detector (the B-Layer, the Layer 1, the Layer 2 and the Disks) were updated using the IBL readout boards. The system has been updated, one layer at a time, giving priority to the next critical layer as the luminosity and level-1 trigger frequency increased. Hence, after IBL, the first critical layer was the Layer 2, then the Layer 1 and finally the B-Layer and the Disks. Eventually, after the technical stop in 2018 the entire ATLAS Pixel Detector will share the same off-detector readout electronics.
In parallel with the commissioning of the upgrade of the current ATLAS Pixel Detector we have designed and fabricated a new readout electronic board to address the requirements of the LHC Phase-2 upgrade. Two batches of prototypes of a Peripheral Component Interconnect Express (PCIe) Gen. 2 boards have been designed and fabricated, the second being a patched version of the first. The first batch was composed of two boards, called Pixel ReadOut Driver (Pixel_ROD) and the second batch was made of five cards called π-LUP. All the boards feature many of the input–output ports and interfaces to address the requirements of the future front-end electronics being developed for the Large Hadron Collider (LHC) Phase-2 upgrade. Thus, the current VERSABUS Module Eurocard (VME) bus will be replaced with the PCIe bus to accommodate the huge increase of throughput (data to be transferred to the DAQ). In this new scenario, the GigaBit Transceiver (GBT) and Aurora protocols are compatible with our boards and the GBTx and RD53A chips will be the first components to be interfaced with. Some laboratory results and measurements are presented here.
•Off-detector readout boards define a huge challenge for the LHC Phase-2 upgrade.•COTS are ever more replacing custom electronics in off-detector readout systems.•Firmware for latest generation FPGAs is a big issue to design and maintain.•PCI-express bus is a proposal for the LHC readout upgrade.
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