The increase of luminosity at High Luminosity LHC will require the introduction of tracker information at Level-1 trigger system for the experiments to maintain an acceptable trigger rate to select ...interesting events despite the one order of magnitude increase in the minimum bias interactions. To extract in the required latency the track information a dedicated hardware has to be used. We present the tests of a prototype system (Pattern Recognition Mezzanine) as core of pattern recognition and track fitting for HL-LHC ATLAS and CMS experiments, combining the power of both Associative Memory custom ASIC and modern Field Programmable Gate Array (FPGA) devices.
In many reflector and lens antennas profiled corrugated circular horns constitute one of the best feed solution thanks to their polarization purity and small size. In this paper, a method for the ...design of these feeds by using an artificial neural network (ANN) approach is described. The results obtained with such an approach are investigated both for the analysis and for the synthesis problem, and compared with the standard methods. This unconventional solution gives a good level of accuracy and shorter processing times especially for the synthesis problem, where there is still a lack of affordable and fully automated procedures.
The increase of luminosity at HL-LHC will require the introduction of tracker information at Level-1 trigger system for the experiments to maintain an acceptable trigger rate to select interesting ...events despite the one order of magnitude increase in the minimum bias interactions. To extract in the required latency the track information a dedicated hardware has to be used. We present the tests of a prototype system (Pattern Recognition Mezzanine) as core of pattern recognition and track fitting for HL-LHC ATLAS and CMS experiments, combining the power of both Associative Memory custom ASIC and modern Field Programmable Gate Array (FPGA) devices.
Testability is a very useful concept in the field of circuit testing and fault diagnosis and can be defined as a measure of the effectiveness of a selected test point set. A very efficient approach ...for automated testability evaluation of analog circuits is based on the use of symbolic techniques. Different algorithms relying on the symbolic approach have been presented in the past by the authors and in this work noteworthy improvements on these algorithms are proposed. The new theoretical approach and the description of the subsequent algorithm that optimizes the testability evaluation from a computational point of view are presented. As a result, in the computer implementation the roundoff errors are completely eliminated and the computing speed is increased. The program which implements this new algorithm is also presented.
The analysis and design of microwave filters obtained by the insertion of cylindrical posts in a rectangular waveguide is in this paper implemented by a neural network approach. The neural ...architecture is able to give an accurate description of the filtering device behaviour in almost real time, whereas the full wave simulator would take several minutes. This kind of approach is suitable to analyse a cascade of multiple posts and to provide a solution for the synthesis of such a filtering device.
The increase of the luminosity in the High Luminosity upgrade of the CERN Large Hadron Collider (HL-LHC) will require the use of Tracker information in the evaluation of the Level-1 trigger in order ...to keep the trigger rate acceptable (i.e.: <; 1MHz). A custom real-time system will be needed to extract the track information within the latency constraints (<;10usec). We developed the prototype of the building block of this system, the Pattern Recognition Mezzanine (PRM) that combines the power of both Associative Memory custom ASICs and modern FPGA devices. The architecture and the functionalities of the PRM are described here.
In the context of the CMS Phase-2 tracker back-end processing system, two mezzanines based on the Zynq Ultrascale+ Multi-Processor System-on-Chip (MPSoC) device have been developed to serve as ...centralized slow control and board management solution for the Serenity-family \textcolor{black}{Advanced Telecommunications Computing Architecture (ATCA)} blades. This paper presents the developments of the MPSoC mezzanines to execute the Intelligent Platform Management Controller (IPMC) software in the real-time capable processors of the MPSoC. In coordination with the Shelf Manager, once full-power is enabled, a CentOS-based Linux distribution is executed in the application processors of the MPSoC, on which EMPButler and the Serenity Management Shell (SMASH) are running.
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