The Serenity-S1 is a Xilinx Virtex Ultrascale+ based Advanced Telecommunications Computing Architecture (ATCA) processing blade that has been optimised for production. It incorporates many ...developments from the Serenity-A and Serenity-Z prototype cards and, where possible, adopts solutions being used across CERN. It also uses many new parts because commonly used parts have disappeared from the market during the semiconductor crisis, with only some returning. Improvements to simplify manufacture, the performance of new components, some of the more difficult aspects of procurement, the performance of production-grade Samtec 25\,Gb/s optical firefly parts, and issues with the rack cooling infrastructure are discussed.
A procedure for the determination of an optimum set of testable components in the fault diagnosis of analog linear circuits is presented. The proposed method has its theoretical foundation in the ...testability concept and in the canonical ambiguity group concept. New considerations relevant to the existence of unique solution in the k-fault diagnosis problem of analog linear circuits are presented, and examples of application of the developed procedure are considered by exploiting a software package based on symbolic analysis techniques.
Finding ambiguity groups in low testability analog circuits Starzyk, J.A.; Pang, J.; Manetti, S. ...
IEEE transactions on circuits and systems. 1, Fundamental theory and applications,
2000-Aug., 2000-08-00, 20000801, Letnik:
47, Številka:
8
Journal Article
This paper discusses a numerically efficient approach to identify complex ambiguity groups for the purpose of analog fault diagnosis in low-testability circuits. The approach presented uses a ...numerically efficient QR factorization technique applied to the testability matrix. Various ambiguity groups are identified. This helps to find unique solution of fault diagnosis equations or identifies which groups of components can be uniquely determined. This work extends results reported earlier in literature, where QR factorization was used in low-testability circuits, significantly increasing efficiency to determine ambiguity groups. A Matlab program that implements this method was integrated with a symbolic analysis program that generates test equations. The method is illustrated on two low-testability electronic circuits. Finally, method efficiency is tested on larger electronic circuits with several hundred tested parameters.
A new approach for the multiple fault location in linear analog circuits is proposed. It presents the characteristic of using classical numerical procedures together with symbolic analysis ...techniques, which is particularly useful in the parametric fault diagnosis field. The proposed approach is based on the k-fault hypothesis and is provided with efficient algorithms for fault location also in the case of low testability circuits. The developed algorithms have been used for realizing a software package prototype which implements a fully automated system for the fault location in linear analog circuits of moderate size.
For the original paper see ibid., vol. 44, no. 3, p. 188-96 (1997). In the aforementioned paper, Spina and Upadhyaya presented a method for the fault diagnosis of analog linear circuits. The method, ...which is based on a white noise generator and an artificial neural network for response analysis, has been applied to circuits of reasonable dimensions, taking into account the effect of the component tolerances. However, the commenters state that the proposed method does not take into account the testability analysis of the circuit under test. They point out that research on testability analysis of linear circuits has been developed by several authors in the last 20 years, and algorithms and programs for testability evaluation have been presented in several publications. It is their opinion that the testability analysis concept could be useful in the approach proposed by Spina and Upadhyaya to improve the quality of the results even further. Here they discuss this possibility.
A symbolic approach for testability evaluation in fault diagnosis of nonlinear analog circuits is presented. The new approach extends the methodologies developed for the linear case to circuits where ...nonlinear components, such as diodes or transistors, are present. The testability evaluation is a fundamental information for the fault diagnosis process, whatever method will be used, also in the nonlinear case. An example of circuit verifying this consideration and the validity of the proposed approach is briefly presented.
The increased complexity of electronic circuits due to technological improvement has caused the need of always more sophisticated testing and fault diagnosis methodologies. However, while for digital ...systems these methodologies have now reached full automation, for analog and mixed signal systems there is a lack of efficient and simple methods in this field. The aim of this work is to present a completely new methodology for the parametric fault diagnosis of linear analog circuits. The new method, which is based on the k-fault diagnosis hypothesis and takes into account tolerances and measurement errors, has been fully automated. The automatic fault diagnosis system has been developed by exploiting symbolic techniques, which permit a significant reduction in the computational complexity.
A novel optimization technique for the parameter identification of microwave monolithic integrated circuits is presented. It is based on a hybrid neural network whose learning process convergence ...allows the validation of the circuit approximated lumped model. The main feature of such a learning process is that no external desired signal is required and the neural network can be considered of the unsupervised type. Furthermore, the neural network output represents the lumped circuit parameter estimation.
