We present a low-jitter digital LC phase-locked loop (PLL) in a standard digital 130-nm CMOS technology, aiming at, but not limited to, clock multiplication in high-speed digital serial interface ...transceivers. The PLL features a fully digital core and a digitally controlled LC oscillator. The use of an integrated programmable coil enables triple-band operation in multi-GHz range (2.2, 3.4, and 4.6 GHz) on a die area as small as 0.21 mm/sup 2/. A new architecture is proposed which improves the authors' previous work and allows to achieve an outstanding long-term jitter lower than 650 fs over the whole frequency range. The PLL consumes 13 mA of current at 1.5-V supply. Its performances compete favorably with the most advanced analog PLLs and are ahead of digital PLLs. Its digital nature makes it easily realizable in the mainstream digital CMOS technologies, robust against noise, and thus ideal for application as a low-jitter clock multiplying unit in digital intensive systems on chip.
The multistep single-path multiplier-free conversion scheme proposed by Fettweis satisfies the requirement of robustness and seems to be attractive for transmultiplexers. This paper describes the ...implementation of a transmultiplexer based on this method using digital signal processors (DSP's). Since most of the currently available or proposed DSP's have sum-of -products type arithmetic units with fixed coefficient wordlengths and since this is not the most favorable approach for implementing wave digital filters (WDF's), a novel DSP will be proposed which is advantageous for WDF's and other more sophisticated digital signal processing algorithms. This DSP makes the multistep single-path multiplier-free conversion scheme a viable alternative to other schemes, also with respect to hardware efficiency and power consumption. The importance of using various simulation programs (in the frequency and the time domain as well as in real time) for supporting the design of the transmultiplexer will be stressed.
Explicit formulas are derived for designing lattice wave digital filters of the most common filter types, for Butterworth, Chebyshev, inverse Chebyshev, and Cauer parameter (elliptic) filter ...responses. Using these formulas a direct top down design method is obtained and most of the practical design problems can be solved without special knowledge of filter synthesis methods. Since the formulas are simple enough also in the case of elliptic filters, the design process is sufficiently simple to serve as basis in the first part (filter design from specs to algorithm) of silicon compilers or applied to high level programmable digital signal processors.
A Possible simplification of digital modulation (carrier multiplication with sine or cosine signal) is discussed. Using the fact that samples of a sine (or cosine) function are periodic under certain ...circumstances, a novel implementation is proposed. Depending on the ratio of sampling and carrier frequencies this implementation can lead to a reduction of cost in comparison with usual methods of implementation. The paper presents a systematic search for the cases where a certain amount of saving in hardware can be achieved.
A fully integrated digital LC PLL for low jitter frequency synthesis in a standard digital 130 nm CMOS technology is presented. The PLL features a fully digital core and a digitally controlled LC ...oscillator. It supports triple-band operation in multi-GHz range (2.1 GHz, 3.3 GHz and 4.4 GHz) with a single programmable coil, resulting in a die area as small as 0.24 mm/sup 2/. While consuming 16 mA of current, the PLL achieves an outstanding long-term jitter of 640 fs, which compares with the most advanced analog PLLs. Its digital nature makes it easily implementable in the main stream digital CMOS technologies, robust against noise and thus ideal for application as a low jitter clock multiplying unit in digital intensive systems on chip (SoCs).
This paper outlines current research trends in the network processor area. It stresses the need for a special class of network processors, namely the network processor for access network (NP4AN) ...sometimes called access processor. It further describes main challenges and architectural choices involved when designing network processors dedicated for use in access network nodes such as DSLAMs (DSL Access Multiplexer). Among others the protocol processing engine, IOs and memory have been considered in more detail. This paper concludes that the main optimization goal for designing such class of network processors should be cost-efficiency.
An area efficient programmable filter structure for sampling rate conversion by an arbitrary ratio for high speed constant-rate /spl Sigma//spl Delta/-converters is proposed. Utilizing cascaded ...lattice wave digital filters in a carry-save architecture with canonic signed-digit coefficients, oversampling ratio and filter characteristic can be programmed using minimum coefficient length. For the implemented 5/sup th/ order Bessel and 4/sup th/ order Butterworth filters used in a variable symbol rate digital subscriber line (DSL) system, the passband edge frequencies can be tuned from 20 kHz to 200 kHz in 2.6 kHz steps with only 25 bits per filter which cannot be achieved with any other IIR or FIR structure. Implementation results of the filters fabricated in a 0.35 /spl mu/m CMOS process using a standard static logic cell library are presented.
An experimental implementation of a small digital filter bank on a commercially available Intel 2920 signal processor is reported. This processor is particularly suitable for implementation of wave ...digital structures since the shift-and-add arithmetic unit is very appropriate for exploiting the low coefficient word-length requirements of these structures. The measured results are in agreement with those expected and confirm the excellent stability properties of wave digital filters.
A new approach to designing polyphase filters with all-pass sections in the individual branches is presented, which is based on a certain number of attenuation zeros in the passband. During the ...optimization procedure of the overall attenuation characteristic, only the frequencies of these attenuation zeros occur as independent variables, therefore, the problem of directly optimizing the large number of filter coefficients is avoided.
N-Port arithmetic unit for DSP Gazsi, L.
ICASSP '82. IEEE International Conference on Acoustics, Speech, and Signal Processing,
1982, Letnik:
7
Conference Proceeding
A new concept in general purpose digital signal processor (DSP) design will be proposed which makes it possible to exhibit the advantages of algorithms optimized for minimum number of addition ...operations. The proposed architecture is specified by an N-port arithmetic unit and N separate memories. The avoidance of all memory conflicts while the memories are simultaneously bandwidth limited, is discussed. It is shown how moderate control and overhead circuitry can be found. Further a discussion about the optimal choice of the arithmetic unit is given. Examples are presented comparing the use of wave digital (Fettweis) implementations and more conventional implementations of fixed point digital filters.
