The use of FPGA circuits in imaging systems increases. They compete with other computing environments. The article describes the indications to be followed while choosing the type of image processing ...computing system taking under consideration the advantages and disadvantages of each technology: general purpose processor, digital signal processor, graphical processing unit, application specific Integrated circuit and field programmable gate array. Attention is drawn to various video transmission standards. The state of research and development trends in the field of FPGA-based image processing are briefly presented. A defining processing performance method for image processing is proposed. It is proven that for a pipeline architecture implemented in FPGA, a linear speedup is achieved and parallel efficiency is equal to one.
Reconfigurable computers are becoming third, after general purpose processors and digital signal processors, programmable computing systems. In the present paper, a new definition of parallelism ...adequate for fine-grain parallel systems is introduced. Computing power requirements for high definition, real-time vision system are discussed. A survey of reconfigurable solutions for image processing and the latest research work carried on at the AGH Laboratory of Biocybernetics are presented.
An universal reprogrammable architecture for implementation of the dedicated image processors (DIP) is presented. This paper considers a new strategy of implementation of the DIP based on replacing ...specialized hardware by a reprogrammable structure. It affords the possibility of creating a flexible image processing system consisting of a reprogrammable hardware structure. The flexible processing system links real-time hardware processing speed with the flexibility of software processing. A new outlook of software and hardware cooperation and co-design in image processing is presented.
In the paper the implementation of classical label component algorithm in Handel-C language has been discussed. The implementation of the image segmentation stage has been realized in real-time in ...the pipeline structure. The process of construction of optimal implementation has been shown, including the algorithm parallelization on one hand and taking advantage of the language features on the other. Each implementation has been verified in hardware and tested by a set of specially designed test images.
Object detection and localization in a video stream is an important requirement for almost all vision systems. In the article a design embedded into a reconfigurable device which is using the ...Histogram of Oriented Gradients for feature extraction and SVM classification for detecting multiple objects is presented. Superior accuracy is achieved by making all computations using single precision 32-bit floating point values in all stages of image processing. The resulting implementation is fully pipelined and there is no need for external memory. Finally a working system able to detect and localize three different classes of objects in color images with resolution 640×480 @ 60fps is presented with a computational performance above 9 GFLOPS.
In the present paper construction of a controller is described, which is used to control the RETINA image processing platform. The 32-bit RETINA card is dedicated to be used for image acquisition, ...processing and analysis. The module resources include Video ADC, Virtex FPGA device, floating point Motorola 96002 DSP and PCI Master interface, what enables the execution of all the operations in real-time. Controller is the main control centre for the module, supervising the modes and phases of its operation, and it is also used as a arbiter for the module's communication resources.
FPGA devices are a perfect platform for implementing image processing algorithms. In the article, an advanced video system is presented, which is able to detect moving objects in video sequences. The ...detection method is using two algorithms. First of all, a multimodal background generation method allows reliable scene modelling in case of rapid changes in lighting conditions and small background movement. Finally a segmentation based on three parameters lightness, colour and texture is applied. This approach allows to remove shadows from the processed image. Authors proposed some improvements and modifications to existing algorithms in order to make them suitable for reconfigurable platforms. In the final system only one, low cost, FPGA device is able to receive data from high speed digital camera, perform a Bayer transform, RGB to CIE Lab colour space conversion, generate a moving object mask and present results to the operator in real-time.
Pedestrian detection is an important feature in an advanced, automated video surveillance system. Unfortunately in most situations cameras are mounted in a way that, due to perspective, walking ...humans are occluded by each other or stationary objects and detecting a whole silhouette is not possible. But heads and shoulders are not occluded in most cases and can be used for object classification (human or not human) or for pedestrian counting. In the article a system implemented in FPGA for head-shoulder detection is presented. It is based on Local Binary Patterns for feature extraction and Support Vector Machines for classification. To reduce the false positives rate, foreground object detection is used as an additional validation criteria. The final system was implemented in a Xilinx Virtex 6 FPGA and is able to process a video stream of resolution 640×480@60 fps in real time.
Video surveillance systems are becoming very common nowadays. Cameras installed in many places are exposed to sabotage or tampering. This can be done by covering the camera lens, changing the focus ...of the camera lens or changing the camera position to prevent proper registration of the surveilled area. This paper describes a hardware implementation of a system that can detect these kind of events. The algorithm is based on background modelling, histograms comparison, edges comparison and analysis of the image's average brightness. In was described in a hardware description language in a pipeline manner and implemented in an FPGA device. Real-time processing of a video stream with a resolution of 640×480@60 frames per second was achieved. Tests performed on several sequences demonstrated the usefulness of the presented solution.
In the demo four video surveillance algorithms implemented on an FPGA platform, running in real-time are presented: detecting intrusions into protected areas, camera tamper detection, head and ...shoulders detection using LBP and SVM and head, people and bicycles detection using HOG and SVM.
