Standard complementary metal-oxide-semiconductor (CMOS) technology and its advanced flavors in the form of FinFETs have propelled the electronic industry to its extraordinary success. While the CMOS ...technology may continue to deliver its remarkably powerful performance to next-generation computing platforms, it is quite clear that in the longer term, it has major challenges in scaling, suffers from power consumption and power density limitations, and may not be amenable to the new demands of the emerging applications. This will require beyond-CMOS technologies to step in and augment CMOS. Whether it is the design of energy-efficient scalable switches for logic design, or nonvolatile memory, or the integration of memory and logic functionalities for general-purpose computers and application-specific accelerators, the need for the application of quantum materials to realize these new microelectronic devices has surged.
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domains walls (DWs) of head-to-head/tail-to-tail (H-H/T-T) type in ferroelectric (FE) materials are of immense interest for a comprehensive understanding of the FE attributes as well as ...harnessing them for new applications. Our first principles calculation suggests that such DW formation in hafnium zirconium oxide (HZO) based FEs depends on the unique attributes of the HZO unit cell, such as polar-spacer segmentation. Cross pattern of the polar and spacer segments in two neighboring domains along the polarization direction (where polar segment of one domain aligns with the spacer segment of another) boosts the stability of such DWs. We further show that low density of oxygen vacancies at the metal-HZO interface and high work function of metal electrodes are conducive for T-T DW formation. On the other hand, high density of oxygen vacancy and low work function of metal electrode favor H-H DW formation. Polarization bound charges at the DW get screened when band bending from depolarization field accumulates holes (electrons) in T-T (H-H) DW. For a comprehensive understanding, we also investigate their FE nature and domain growth mechanism. Our analysis suggests that a minimum thickness criterion of domains has to be satisfied for the stability of H-H/T-T DW and switching of the domains through such DW formation.
Collective interactions in functional materials can enable novel macroscopic properties like insulator-to-metal transitions. While implementing such materials into field-effect-transistor technology ...can potentially augment current state-of-the-art devices by providing unique routes to overcome their conventional limits, attempts to harness the insulator-to-metal transition for high-performance transistors have experienced little success. Here, we demonstrate a pathway for harnessing the abrupt resistivity transformation across the insulator-to-metal transition in vanadium dioxide (VO2), to design a hybrid-phase-transition field-effect transistor that exhibits gate controlled steep ('sub-kT/q') and reversible switching at room temperature. The transistor design, wherein VO2 is implemented in series with the field-effect transistor's source rather than into the channel, exploits negative differential resistance induced across the VO2 to create an internal amplifier that facilitates enhanced performance over a conventional field-effect transistor. Our approach enables low-voltage complementary n-type and p-type transistor operation as demonstrated here, and is applicable to other insulator-to-metal transition materials, offering tantalizing possibilities for energy-efficient logic and memory applications.
In this paper, we describe an improved SPICE model for the negative capacitance field-effect transistor (NCFET). According to the law of conservation of charge, the model is built based on the ...relationship between the gate charge of the MOSFET and the charge reserved by the ferroelectric layer and includes the parasitic resistance and capacitance into consideration. Based on the model, the drain-induced barrier lowering (DIBL) and the negative resistance (NR) of the NCFET are analyzed. Finally, taking two well-known analog blocks (the current mirror and the latch comparator) for example, impacts of the DIBL effect and the NR property on analog circuit performances are discussed. Thanks to utilization of the NR feature, not only can impacts of the DIBL effect and the channel-length modulation (CLM) effect be alleviated to improve the mirroring accuracy, but also the comparison speed of the latch comparator be accelerated.
Negative-capacitance FETs (NCFETs) are a promising candidate for low-power circuits with intrinsic features, e.g., the steep switching slope. Prior works have shown potential for enabling low-power ...digital logic and memory design with NCFETs. Yet, it is still not quite clear how to harness these new features of NCFETs for analog functionalities. This article provides more insights into the circuit design space with new device characteristics and investigates its deployment in analog circuits, specifically, time-domain analog-to-digital converters (ADCs) and phase-locked loops (PLLs). We propose and optimize a novel digital-based clocked comparator and a capacitor-based voltage-to-time converter (VTC), which are essential building blocks in ADCs and PLLs. Evaluation results show beyond-FinFET comparison speed and enhanced linearity for the proposed NCFET-based clocked comparator and VTC, respectively. Such improvement is achieved by exploiting the steeper slope and increased output impedance of NCFETs. More details on design details and a discussion are provided in this article.
Hybrid-phase-transition FETs (Hyper-FETs) are recently proposed steep switching devices that utilize the phase transition materials (PTM) to achieve a boost in the ratio of ON (I ON ) and OFF ...currents (I OFF ). Prototypical demonstrations of the Hyper-FET have shown performance improvement in comparison with conventional transistors, which motivates the evaluation of its device-circuit design space. In part I, we analyze the device aspects establishing the effects of the resistivity and phase transition thresholds of the PTM on the characteristics of Hyper-FETs. Our analysis shows that the ratio of insulating and metallic state resistivity (ρ INS and ρ MET , respectively) of the PTM needs to be higher than the ION/IOFF of its host transistor to achieve performance improvement in Hyper-FET. For a host transistor with I OFF = 0.051μA/μm and I ON = 191.5μA/μm, ρ MET <;~ 2 × 10 -3 Ω.cm and ~7.5 Ω.cm<; ρ INS <; 20000Ω.cm is required to achieve proper device functionality with a boost in I ON /I OFF . Additionally, we establish the ranges of phase transition thresholds that yield proper functionality of the Hyper-FETs considering different I OFF targets. The methodology of choosing appropriate PTM geometry to achieve the target device characteristics is also described. We show that with proper design, Hyper-FETs achieve 94% larger I ON at iso-I OFF compared with a FinFET. We examine the circuit design aspects of Hyper-FET in part II.
In this paper, we analyze and optimize FinFETs with asymmetric drain spacer extension (ADSE) that introduces a gate underlap only on the drain side. We present a physics-based discussion of ...current-voltage relationships, short channel effects, and leakage and show the application of ADSE FinFETs in 6T static random access memory (SRAM) bit cell. By exploiting asymmetry in current, we show that it is possible to achieve improvement in both read and write stability for the 6T SRAM bit cell, along with reduction in cell leakage at the cost of negligible increase in access time and area. We also propose a general circuit-aware device optimization methodology for SRAM design. We use this methodology to optimize the underlap in ADSE FinFETs. Compared to conventional FinFETs, we achieve 57% reduction in leakage, 11% improvement in read static-noise margin, and 6% improvement in write margin, with 7% increase in access time and cell area.
Valley-spin hall (VSH) effect in monolayer WSe2 has been shown to exhibit highly beneficial features for nonvolatile memory (NVM) design. Key advantages of VSH-based magnetic random access memory ...(VSH-MRAM) over spin orbit torque (SOT)-MRAM include access transistor-less compact bit-cell and low-power switching of perpendicular magnetic anisotropy (PMA) magnets. Nevertheless, large device resistance in the read path (<inline-formula> <tex-math notation="LaTeX">R_{S} </tex-math></inline-formula>) due to low mobility of WSe2 and Schottky contacts deteriorates sense margin (SM), offsetting the benefits of VSH-MRAM. To address this limitation, we propose another flavor of VSH-MRAM that (while inheriting most of the benefits of VSH-MRAM) achieves lower <inline-formula> <tex-math notation="LaTeX">R_{S} </tex-math></inline-formula> in the read path by electrically isolating the read and write terminals. This is enabled by coupling VSH with electrically isolated but magnetically coupled PMA magnets via interlayer exchange coupling. Designing the proposed devices using object-oriented micromagnetic framework (OOMMF) simulation, we ensure the robustness of the exchange-coupled PMA system under process variations. To maintain a compact memory footprint, we share the read access transistor across multiple bit-cells. Compared with the existing VSH-MRAMs, our design achieves 39%-42% and 36%-46% reduction in read time and energy, respectively, along with <inline-formula> <tex-math notation="LaTeX">1.1\times - 1.3\times </tex-math></inline-formula> larger SM at a comparable area. This comes at the cost of <inline-formula> <tex-math notation="LaTeX">1.7\times </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">2.0\times </tex-math></inline-formula> increase in write time and energy, respectively. Thus, the proposed design is suitable for applications in which reads are more dominant than writes.
Abstract
To understand and harness the physical mechanisms of ferroelectric hafnium zirconium oxide (HZO)‐based devices, there is a need for clear understanding of domain interactions, their ...dynamics, negative capacitance effects, and other multidomain characteristics. These crucial attributes depend on the coupling between neighboring domains quantified by the gradient energy coefficient (
g
). Furthermore, HZO has unique orientation‐dependent lateral multidomain configurations. To develop an in‐depth understanding of multidomain effects, there is a need for a thorough analysis of
g
. In this work, the energetics of multidomain configurations and domain growth mechanism corresponding to lateral domain walls (DWs) of HZO are analyzed and gradient energy coefficients are quantified using first‐principles density functional theory calculations. These results indicate that one lateral direction exhibits the following characteristics: i) DW is ultra‐sharp and domain growth occurs unit‐cell‐by‐unit‐cell, ii) the value of
g
is negative and in the order of 10
−12
V m
3
C
−1
, and iii)
g
reduces (increases) with compressive (tensile) strain. In contrast, in the other lateral direction, the following attributes are observed: i) DW is gradual and domain growth occurs in quanta of half‐unit‐cell, ii)
g
is positive and in the order of 10
−10
V m
3
C
−1
, and iii)
g
increases (reduces) with compressive (tensile) strain.
Hyper-FET, an emerging device with unconventional characteristics, exhibits sub-kT/q switching and can attain higher ON current (I ON ) than standard FinFETs with matched OFF current (I OFF ). In ...continuation to the insights on the device level design methodology conveyed in part I 1, here we analyze the circuit implications of the unique characteristics of Hyper-FETs, such as hysteresis and abrupt switching. We provide a comprehensive discussion on the design of Hyper-FET-based circuit primitives, such as inverter, NOR and NAND gates. We emphasize on tailoring the hysteresisto avoid functional failure in logic circuits and deduce the correspondence between hysteresis observed in the device and circuit characteristics. To complement the device level constraints presented in part I, here we present additional stringencies for material parameters to aid in designing Hyper-FET-based logic gates with regenerative property and rail-to-rail swing. Our analysisindicates that, at low V DD (<;0.3 V), properly designed Hyper-FETbased inverters can exhibit 25%-68% less energy at isodelay (compared with FinFET-based CMOS inverters). We also provide targets for future material exploration.
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