A new approach to monolithic pixel detectors, based on silicon on insulator (SOI) wafers with high resistivity substrate, is being pursued by the CERN RD19 collaboration. The fabrication methods and ...the results of the electrical evaluation of the SOI-MOSFET devices and of the detector structures fabricated in the bulk are reported. The leakage current of the high-resistivity PIN-diodes is kept of the order of 5 to 10 nA/cm/sup 2/. The SOI preparation processes employed-SIMOX (separation by implantation of oxygen) and ZMR (zone melting recrystallization)-produce working electronic circuits, and appear to be compatible with the fabrication of detectors of suitable quality.< >
An asynchronous version of a binary pixel readout circuit has been implemented in an array with 16 columns at 500 mu m pitch and 63 rows at 75 mu m pitch. This readout chip has been bonded with ...solder bumps to a silicon detector with matching pixel elements. Event information in a pixel can be strobed into a local memory by a trigger signal and subsequently read out. Without a strobe the information in this memory is continuously cleared. The complete hybrid detector has been successfully tested with ionizing particles from a radioactive source. Three such devices have been used in the CERN heavy ion experiment WA94 in the Omega spectrometer where they recorded particle tracks from high multiplicity /sup 32/S interactions.< >
We present experimental results from a fast charge amplifier and a wideband analog buffer processed in the DMILL BiCMOS-JFET radhard SOI technology and irradiated up to 4.5/spl times/10/sup 14/ ...protons/cm/sup 2/. In parallel, we have irradiated elementary transistors. These components were biased and electrical measurements were done 30 min after beam stop. By evaluating variations of main SPICE parameters, i.e., threshold voltage shift for CMOS and current gain variation for bipolar transistors, we have simulated the wideband analog buffer at different doses. These SPICE simulations are in good agreement with measured circuit degradations. The behavior of the charge amplifier is consistent with extraction of transconductance and pinch-off voltage shift of the PJFET.< >
High Energy Physics experiments under preparation at CERN (Geneva, Switzerland) with the future LHC (Large Hadron collider) require a fast, low noise, very rad-hard, mixed analog-digital ...microelectronics VLSI technology. Readout electronics designed using such a technology for the central parts of the LHC particle detectors must withstand more than 10 Mrad (SiO/sub 2/) and 10/sup 14/ neutrons/cm/sup 2/ over 10 years of operation. We present here recent results obtained with a new rad-hard analog-digital technology called DMILL, which monolithically integrates NPN bipolar, CMOS and P-JFET transistors, and which has been specifically developed to fulfill the severe constraints of LHC detector readout circuits.
The authors present results obtained on a rad-hard mixed analog-digital technology that integrates monolithically complementary MOS (CMOS) transistors, complementary junction FETs (CJFETs), and ...complementary bipolar transistors (C-bipolars). This technology is expected to satisfy the hard constraints of Large Hadron Collider (LHC) detector electronics. These three families of transistors have been chosen to offer large flexibility of design. MOS and bipolar transistors provide electrical characteristics close to those of modern BiCMOS technologies and will allow the design on the same chip of both analog and digital fast rad-hard circuits. JFET transistors will permit designs of low-noise very rad-hard circuits for room or cryogenic temperature operation. The results show devices with rad-hard performances against neutrons and gamma particles in the range of 1*10/sup 14/ n/cm/sup 2/ (1 MeV) and 10 Mrads (SiO/sub 2/), well suited to LHC detector requirements. JFETs, which have shown a low sensitivity to protons (500 MeV) up to 1*10/sup 14/, are very rad-hard against ionizing dose as well as displacement damages.< >
Radiation tolerance of single-sided silicon microstrips
Nuclear instruments and methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment/Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
02/1994
Journal Article
An asynchronous version of a binary pixel readabout circuit has been implemented in an array with 16 columns at 500 mu m pitch and 63 rows at 75 mu m pitch. This readabout chip has been bonded with ...solder bumps to a silicon detector with matching pixel elements. Event information in a pixel can be strobed into a local memory by a trigger signal and subsequently read out. Without a strobe the information is continuously cleared. The complete hybrid detector has been successfully tested with ionizing particles from a radioactive source. Three such devices have been put in the CERN heavy-ion experiment WA94 in the Omega spectrometer, where they recorded particle tracks from high-multiplicity /sup 32/S interactions. Preliminary data indicate a noise of approximately 60 e/sup -/ and a threshold spread of approximately 500 e/sup -/. The timing characteristics are adequate for a fixed-target experiment.< >
High energy physics experiments under preparation at CERN (Geneva, Switzerland) with the future LHC (Large Hadron Collider) require a fast, low noise, very rad-hard, mixed analog-digital ...microelectronics VLSI technology. Readout electronics designed using such a technology for the central parts of the LHC particle detectors must withstand more than 10 Mrad (SiO/sub 2/) and 10/sup 14/ neutrons/cm/sup 2/ over 10 years of operation. We are presenting here recent results obtained with a new rad-hard analog-digital technology called DMILL, which monolithically integrates NPN bipolar, CMOS and P-JFET transistors, and which has been specifically developed to fulfil the severe constraints of LHC detectors readout circuits.
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