Reverse engineering is a burning issue in Integrated Circuit (IC) design and manufacturing. In the semiconductor industry, it results in a revenue loss of billions of dollars every year. In this ...work, an area efficient, high-performance IC camouflaging technique is proposed at the physical design level to combat the integrated circuit's reverse engineering. An attacker may not identify various logic gates in the layout due to similar image output. In addition, a dummy or true contact-based technique is implemented for optimum outcomes. A library of gates is proposed that contains the various camouflaged primitive gates developed by a combination of using the metal routing technique along with the dummy contact technique. This work shows the superiority of the proposed technique's performance matrix with those of existing works regarding resource burden, area, and delay. The proposed library is expected to make open source to help ASIC designers secure IC design and save colossal revenue loss.
Advanced Encryption Standard (AES) is the most secured ciphertext algorithm that is unbreakable in a software platform's reasonable time. AES has been proved to be the most robust symmetric ...encryption algorithm declared by the USA Government. Its hardware implementation offers much higher speed and physical security than that of its software implementation. The testability and hardware Trojans are two significant concerns that make the AES chip complex and vulnerable. The problem of testability in the complex AES chip is not addressed yet, and also, the hardware Trojan insertion into the chip may be a significant security threat by leaking information to the intruder. The proposed method is a dual-mode self-test architecture that can detect the hardware Trojans at the manufacturing test and perform an online parametric test to identify parametric chip defects. This work contributes to partitioning the AES circuit into small blocks and comparing adjacent blocks to ensure self-referencing. The detection accuracy is sharpened by a comparative power ratio threshold, determined by process variations and the accuracy of the built-in current sensors. This architecture can reduce the delay, power consumption, and area overhead compared to other works.
This paper presents the design of a Built-in-self-Test (BIST) implemented Advanced Encryption Standard (AES) cryptoprocessor Application Specific Integrated Circuit (ASIC). AES has been proved as the ...strongest symmetric encryption algorithm declared by USA Govt. and it outperforms all other existing cryptographic algorithms. Its hardware implementation offers much higher speed and physical security than that of its software implementation. Due to this reason, a number of AES cryptoprocessor ASIC have been presented in the literature, but the problem of testability in the complex AES chip is not addressed yet. This research introduces a solution to the problem for the AES cryptoprocessor ASIC implementing mixed-mode BIST technique, a hybrid of pseudo-random and deterministic techniques. The BIST implemented ASIC is designed using IEEE industry standard Hardware Description Language(HDL). It has been simulated using Electronic Design Automation (EDA)tools for verification and validation using the input-output data from the National Institute of Standard and Technology (NIST) of the USA Govt. The simulation results show that the design is working as per desired functionalities in different modes of operation of the ASIC. The current research is compared with those of other researchers, and it shows that it is unique in terms of BIST implementation into the ASIC chip.
Blockchain technology has gained widespread popularity due to its robust security features, making it an attractive solution for various applications such as cryptocurrency, healthcare, supply chain ...management, and asset administration. However, limited research has been conducted on the limitations and security issues associated with blockchain technology. In this research article, we focus on the key limitations of blockchain technology, namely, throughput and storage optimization. In this work, we address these issues by designing a faster and less storage-dependent blockchain system while maintaining the security and essential features of blockchain technology. By combining the dual blockchain concept with the Interplanetary File System (IPFS), a higher number of transactions can be accommodated within a single block. This leads to amplified throughput and diminished storage requirements. IPFS is harnessed to circumvent storage limitations and enhance overall transaction throughput. Our proposed system is implemented in real-time, resulting in significantly increased throughput and reduced storage requirements. Our findings demonstrate that this system is suitable for use in both cryptocurrencies and real-life applications.
Due to outsourcing of numerous stages of the IC manufacturing process to different foundries, the security risk, such as hardware Trojan becomes a potential threat. In this paper, we present a layout ...aware localized hardware Trojan detection method that magnifies the detection sensitivity for small Trojan in power-based side-channel analysis. A scan segmentation approach with a modified launch-on-capture (LoC) transition delay fault test pattern application technique is proposed so as to maximize the dynamic power consumption of any target region. The new architecture allows activating any target region and keeping others quiet, which reduces total circuit toggling activity. We evaluate our approach on ISCAS89 benchmark and two practical circuits to demonstrate its effectiveness in side-channel analysis.
The performance of Advanced Encryption Standard (AES) mainly depends on speed, area and power. The S-box represents an important factor that affects the performance of AES on each of these factors. A ...number of techniques have been presented in the literature, which have attempted to improve the performance of the S-box byte-substitution. This paper proposes a new S-box architecture, defining it as ultra low power, robustly parallel and highly efficient in terms of area. The architecture is discussed for both CMOS and FPGA platforms, and the pipelined architecture of the proposed S-box is presented for further time savings and higher throughput along with higher hardware resources utilization. A performance analysis and comparison of the proposed architecture is also conducted with those achieved by the existing techniques. The results of the comparison verify the outperformance of the proposed architecture in terms of power, delay and size.
Introduction
Virtual reality (VR) cycling exercise was developed as a physical rehabilitation therapy to impair the deficit on motoric function and cardiorespiratory fitness on post-stroke patients ...with lower extremity disorder. This study aims to figure out the effectiveness of VR cycling exercise towards the impairment of lower extremity motoric function and cardiorespiratory fitness on the post-stroke patients.
Methods
This study engaged 15 people chosen through a purposive sampling method which were divided into 8 intervention groups of post-stroke patients without comorbid (post stroke ≥ 2 years) and 7 healthy people in a control group. Fugl Meyer assessment was used to decide the participation of the patients. To assess the lower extremity motoric functions, timed up-and-go test (TUGT) was carried out. 6-minute walking test (6-MWT) was conducted to assess the function of gaits. VO2max was carried out to assess the cardiorespiratory fitness. VR cycling exercise had been conducted for 3 months, twice a week.
Results
Both groups performed significant difference (p < 0.05) in terms of balance, gait ability, and cardiorespiratory fitness. The decrease of TUGT score and increase of 6-MWT and VO2max tests’ scores of the intervention group obtained after having VR cycling exercise was significantly bigger than it was before taking the exercise. The group of post-stroke patients were able to take the exercise in 40–60 minutes/time of exercise.
Conclusions
VR cycling exercise is such an effective intervention to increase motoric function and cardiorespiratory fitness on chronic post-stroke patients. Therefore, taking VR cycling exercise is recommended for a stroke rehabilitation and clinical practice purposes.
Addressing the challenge of high detection sensitivity in the presence of process variation is crucial for hardware Trojan detection through post-silicon side-channel analysis. In this work, we ...introduce an effective and efficient approach for Trojan detection, even in the face of increased systematic and random process variations. To enhance detection sensitivity, our method involves: i) Activating small regions to amplify Trojan-to-circuit activity, ii) comparing power levels from neighboring regions within the same chip, ensuring a consistent trend in both interdie and intra-die systematic process variations and iii) selecting random variation-tolerant test patterns by analyzing glitch effects through Monte Carlo simulation. We propose a fine-grain, low-cost circuit partitioning algorithm and suggest an evaluation method for detection sensitivity based on a glitch variation-aware detection threshold. Our approach is evaluated on ISCAS'89 benchmark circuits, encompassing both combinational and sequential Trojan types. Through an analysis of variation thresholds and experiments with Trojan-inserted circuits across diverse process variation levels, we demonstrate high detection sensitivity.
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