This paper describes the behavior of top-gated transistors fabricated using carbon, specifically epitaxial graphene on SiC, as the active material. Although graphene devices have been built before, ...in this paper, we provide the first demonstration and systematic evaluation of arrays of a large number of transistors produced using standard microelectronics methods. The graphene devices presented feature high-k dielectric, mobilities up to 5000 cm 2 /Vldr s, and I on /I off ratios of up to seven, and are methodically analyzed to provide insight into the substrate properties. Typical of graphene, these micrometer-scale devices have negligible band gaps and, therefore, large leakage currents.
The effective work function of a reactively sputtered TiN metal gate is shown to be tunable from 4.30 to 4.65 eV. The effective work function decreases with nitrogen flow during reactive sputter ...deposition. Nitrogen annealing increases the effective work function and reduces D it . Thinner TiN improves the variation in effective work function and reduces gate dielectric charge. Doping of the polysilicon above the TiN metal gate with B or P has negligible effect on the effective work function. The work-function-tuned TiN is integrated into ultralow-power fully depleted silicon-on-insulator CMOS transistors optimized for subthreshold operation at 0.3 V. The following performance metrics are achieved: 64-80-mV/dec subthreshold swing, PMOS/NMOS on-current ratio near 1, 71% reduction in C gd , and 55% reduction in V t variation when compared with conventional transistors, although significant short-channel effects are observed.
The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The essential elements of the 3-D technology are integrated circuit fabrication on ...silicon-on-insulator wafers, precision wafer-wafer alignment using an in-house-developed alignment system, low-temperature wafer-wafer bonding to transfer and stack active circuit layers, and interconnection of the circuit layers with dense-vertical connections with sub-Omega 3-D via resistances. The 3-D integration process is described as well as the properties of the four enabling technologies. The wafer-scale 3-D technology imposes constraints on the placement of the first lithographic level in a wafer-stepper process. Control of wafer distortion and wafer bow is required to achieve submicrometer vertical vias. Three-tier digital and analog 3-D circuits were designed and fabricated. The performance characteristics of a 3-D ring oscillator, a 1024 times 1024 visible imager with an 8-mum pixel pitch, and a 64 times 64 Geiger-mode laser radar chip are described
Ultralow-power electronics will expand the technological capability of handheld and wireless devices by dramatically improving battery life and portability. In addition to innovative low-power design ...techniques, a complementary process technology is required to enable the highest performance devices possible while maintaining extremely low power consumption. Transistors optimized for subthreshold operation at 0.3 V may achieve a 97% reduction in switching energy compared to conventional transistors. The process technology described in this article takes advantage of the capacitance and performance benefits of thin-body silicon-on-insulator devices, combined with a workfunction engineered mid-gap metal gate.
This paper presents results of fully packaged RF microelectromechanical (RF-MEM) switches including capacitive series, series-shunt, and single-pole-four-throw (SP4T) switch nodes. The RF-MEM ...capacitive switches are packaged using recently developed wafer scale low-loss and broadband packaging technology developed at MIT Lincoln Laboratory, Lexington, MA. A packaged series capacitive switch with 0.11-dB insertion loss and better than 19-dB isolation, a series-shunt packaged capacitive switch with 0.3-dB insertion loss and better than 54 dB isolation, and an SP4T switch with less than 0.26-dB insertion loss and better than 25-dB isolation at 20 GHz are reported. Detailed reliability, radiation, cryogenic, and power-handling data are also presented.
A 1024/spl times/1024 integrated image sensor with 8 /spl mu/m pixels, is developed with 3D fabrication in 150 mm wafer technology. Each pixel contains a 2 /spl mu/m/spl times/2 /spl mu/m/spl ...times/7.5 /spl mu/m 3D via to connect a deep depletion, 100% fill-factor photodiode layer to a fully depleted SOI CMOS readout circuit layer. Pixel operability exceeds 99.9%, and the detector has a dark current of <3 nA/cm/sup 2/ and pixel responsivity of /spl sim/9 /spl mu/V/e at room temperature.
Graphene transistors are made by transferring a thin graphene film grown on Ni onto an insulating SiO 2 substrate. The properties and integration of these graphene-on-insulator transistors are ...presented and compared to the characteristics of devices made from graphitized SiC and exfoliated graphene flakes.
Using a CCD/CMOS technology, a fully parallel 4*4 focal plane processor, which performs image acquisition, smoothing, and segmentation, has been fabricated and characterized. In this chip, image ...brightness is converted into signal charge using charge-coupled-device (CCD) imaging techniques. The Gaussian smoothing operation is approximated by the repeated application of a simple nearest-neighbor binomial convolution mask, realizing the first known use of a true two-dimensional charge division and transfer process. The design allows full control of the spatial extent of the smoothing operation, and incorporates segmentation circuits with global variable threshold control at each pixel location to preserve edges in the image. The processed image is read out using a standard CCD clocking scheme.< >
A review of recent efforts to develop photoresist materials and processes for 193-nm (ArF excimer laser) photolithography is reported. Three categories of resist processes are discussed: (1) ...single-layer resists based on acrylate polymers, (2) silicon-polymer bilayer resists, and (3) surface-imaged positive-tone silylation resist processes. To date, materials have been developed for each process which exhibit resolution to better than 0.20μm with sensitivities less than 50mJ/cm2.
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