Positron tracking detector for J-PARC muon g−2/EDM experiment Yamanaka, T.; Aoyagi, T.; Ikeda, H. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
04/2020, Letnik:
958
Journal Article
Recenzirano
The positron tracking detector is developed for the J-PARC muon g−2/EDM (E34) experiment. It uses silicon strip sensors for positron detection and signals from sensors are transferred to the ...front-end readout system via flexible printed circuits (FPCs) glued on the sensors. The front-end readout system consists of application specific integrated circuits (ASICs) on FPCs and the field-programmable gate array (FPGA)-based readout board. Mass production of silicon strip sensors is ongoing. Designs of the FPC on the sensor and the front-end ASIC were fixed and their mass production has been started. Development of other detector components are also ongoing. The status of these developments and fabrications are presented.
This paper describes the recent development of a gigabit data transmitter for the Belle-II pixel detector (PXD). The PXD is an innermost detector currently under development for the upgraded KEK-B ...factory in Japan. The PXD consists of two layers of DEPFET sensor modules located at 1.8 and 2.2cm radii. Each module is equipped with three different ASIC types mounted on the detector substrate with a flip-chip technique: (a) SWITCHER for generating steering signals for the DEPFET sensors, (b) DCD for digitizing the signal currents, and (c) DHP for performing data processing and sending the data off the module to the back-end data handling hybrid via ∼40cm Kapton flex and 12–15m twisted pair (TWP) cables. To meet the requirements of the PXD data transmission, a prototype of the DHP data transmitter has been developed in a 65-nm standard CMOS technology. The transmitter test chip consists of current-mode logic (CML) drivers and a phase-locked loop (PLL) which generates a clock signal for a 1.6Gbit/s output data stream from an 80cm reference clock. A programmable pre-emphasis circuit is also implemented in the CML driver to compensate signal losses in the long cable by shaping the transmitted pulse response. The jitter performance was measured as 25ps (1σ distribution) by connecting the chip with 38cm flex and 10m TWP cables.
We report on the recent development of a 32-channel low-noise analog front-end ASIC "KW03" for hard X-ray and gamma-ray detectors. The ASIC aims for the readout of strip or pixel (pad) detectors ...utilizing silicon and cadmium telluride (CdTe) as detector materials. Each readout channel includes a charge-sensitive amplifier, bandpass filters and a sample-and-hold circuit. It also includes a leakage current compensation and pole-zero cancellation circuits to meet the various detector requirements. The equivalent noise level of a typical channel reaches 89 e - @ 0 pF (rms) and shows an input-capacitance characteristic of 7.5 e - /pF between 0 pF and 10 pF with a power consumption of 3 mW per channel. We mounted the ASIC on a low-temperature co-fired ceramic (LTCC) package and evaluated the spectral performance by combining with a CdTe diode detector. As a result, the gamma-ray spectrum of radioactive source 241 Am was obtained with a good energy resolution of 2.23 keV (FWHM) for gamma rays of 59.5 keV at -20°C.
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