A differential single-port switched-RC N-path filter with band-pass characteristic is proposed. The switching frequency defines the center frequency, while the RC-time and duty cycle of the clock ...define the bandwidth. This allows for high-Q highly tunable filters which can for instance be useful for cognitive radio. Using a linear periodically time-variant (LPTV) model, exact expressions for the filter transfer function are derived. The behavior of the circuit including non-idealities such as maximum rejection, spectral aliasing, noise and effects due to mismatch in the paths is modeled and verified via measurements. A simple RLC equivalent circuit is provided, modeling bandwidth, quality factor and insertion loss of the filter. A 4-path architecture is realized in 65 nm CMOS. An off-chip transformer acts as a balun, improves filter-Q and realizes impedance matching. The differential architecture reduces clock-leakage and suppresses selectivity around even harmonics of the clock. The filter has a constant -3 dB bandwidth of 35 MHz and can be tuned from 100 MHz up to 1 GHz. Over the whole band, IIP3 is better than 14 dBm, P 1dB =2 dBm and the noise figure is 3-5 dB, while the power dissipation increases from 2 mW to 16 mW (only clocking power).
A software-defined radio (SDR) receiver with improved robustness to out-of-band interference (OBI) is presented. Two main challenges are identified for an OBI-robust SDR receiver: out-of-band ...nonlinearity and harmonic mixing. Voltage gain at RF is avoided, and instead realized at baseband in combination with low-pass filtering to mitigate blockers and improve out-of-band IIP3. Two alternative ¿iterative¿ harmonic-rejection (HR) techniques are presented to achieve high HR robust to mismatch: a) an analog two-stage polyphase HR concept, which enhances the HR to more than 60 dB; b) a digital adaptive interference cancelling (AIC) technique, which can suppress one dominating harmonic by at least 80 dB. An accurate multiphase clock generator is presented for a mismatch-robust HR. A proof-of-concept receiver is implemented in 65 nm CMOS. Measurements show 34 dB gain, 4 dB NF, and + 3.5 dBm in-band IIP3 while the out-of-band IIP3 is +16 dBm without fine tuning. The measured RF bandwidth is up to 6 GHz and the 8-phase LO works up to 0.9 GHz (master clock up to 7.2 GHz). At 0.8 GHz LO, the analog two-stage polyphase HR achieves a second to sixth order HR > 60 dB over 40 chips, while the digital AIC technique achieves HR > 80 dB for the dominating harmonic. The total power consumption is 50 mA from a 1.2 V supply.
N-path switched-RC circuits can realize filters with very high linearity and compression point while they are tunable by a clock frequency. In this paper, both differential and single-ended N-path ...notch filters are modeled and analyzed. Closed-form equations provide design equations for the main filtering characteristics and nonidealities such as: harmonic mixing, switch resistance, mismatch and phase imbalance, clock rise and fall times, noise, and insertion loss. Both an eight-path single-ended and differential notch filter are implemented in 65-nm CMOS technology. The notch center frequency, which is determined by the switching frequency, is tunable from 0.1 to 1.2 GHz. In a 50-Ω environment, the N-path filters provide power matching in the passband with an insertion loss of 1.4-2.8 dB. The rejection at the notch frequency is 21-24 dB, P 1 dB > +2 dBm, and IIP3 > +17 dBm.
This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses ...step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately 115 225 Unknown character mu hbox m 2 . At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 Unknown character mu hbox W and achieves an energy efficiency of 4.4 fJ/conversion-step.
An inductorless low-noise amplifier (LNA) with active balun is proposed for multi-standard radio applications between 100 MHz and 6 GHz. It exploits a combination of a common-gate (CGH) stage and an ...admittance-scaled common-source (CS) stage with replica biasing to maximize balanced operation, while simultaneously canceling the noise and distortion of the CG-stage. In this way, a noise figure (NF) close to or below 3 dB can be achieved, while good linearity is possible when the CS-stage is carefully optimized. We show that a CS-stage with deep submicron transistors can have high IIP2, because the nu gs ldr nu ds cross-term in a two-dimensional Taylor approximation of the I DS (V GS , V DS ) characteristic can cancel the traditionally dominant square-law term in the I DS (V GS ) relation at practical gain values. Using standard 65 nm transistors at 1.2 V supply voltage, we realize a balun-LNA with 15 dB gain, NF < 3.5 dB and IIP2 > +20 dBm, while simultaneously achieving an IIP3 > 0 dBm. The best performance of the balun is achieved between 300 MHz to 3.5 GHz with gain and phase errors below 0.3 dB and plusmn2 degrees. The total power consumption is 21 mW, while the active area is only 0.01 mm 2 .
This paper presents phase-locked loop (PLL) reference-spur reduction design techniques exploiting a sub-sampling phase detector (SSPD) (which is also referred to as a sampling phase detector). The ...VCO is sampled by the reference clock without using a frequency divider and an amplitude controlled charge pump is used which is inherently insensitive to mismatch. The main remaining source of the VCO reference spur is the periodic disturbance of the VCO by the sampling at the reference frequency. The underlying VCO sampling spur mechanisms are analyzed and their effect is minimized by using dummy samplers and isolation buffers. A duty-cycle-controlled reference buffer and delay-locked loop (DLL) tuning are proposed to further reduce the worst case spur level. To demonstrate the effectiveness of the proposed spur reduction techniques, a 2.21 GHz PLL is designed and fabricated in 0.18 μm CMOS technology. While using a high loop-bandwidth-to-reference-frequency ratio of 1/20, the reference spur measured from 20 chips is <; -80 dBc. The PLL consumes 3.8 mW while the in-band phase noise is -121 dBc/Hz at 200 kHz and the output jitter integrated from 10 kHz to 100 MHz is 0.3ps rms .
This paper presents a set of circuit techniques to achieve high data rate point-to-point communication over long on-chip RC-limited wire-pairs. The ideal line termination impedances for a flat ...transfer function with linear phase (pure delay) are derived, using an s-parameter wire-pair model. It is shown that a driver with series capacitance on the one hand and a resistive load on the other, are fair approximations of these ideal terminations in the frequency range of interest. From a perspective of power efficiency, a capacitive driver is preferred, as the series capacitance reduces the voltage swing along the line which reduces dynamic power consumption. To reduce cross-talk and maintain data integrity, parallel differential interconnects with alternatingly one or two twists are used. In combination with a low offset dynamic sense amplifier at the receiver, and a low-power decision feedback equalization technique with analog feedback, gigabit communication is demonstrated at very low power consumption. A point-to-point link on a 90 nm CMOS test chip achieves 2 Gb/s over 10 mm long interconnects, while consuming 0.28 pJ/bit corresponding to 28 fJ/bit/mm, which is much lower than competing designs.
A low-power interferer-robust mixer-first receiver front end that uses a novel capacitive stacking technique in a bottom-plate N-path filter/mixer is proposed. Capacitive stacking is achieved by ...reading out the voltage from the bottom plate of N-path capacitors instead of their top plate, which provides a 2x voltage gain after downconversion. A step-up transformer is used to improve the out-of-band (OOB) linearity performance of small switches in the N-path mixer, thereby reducing the power consumption of switch drivers. This article explains the concept of implicit capacitive stacking and analyzes its transfer characteristics. A prototype chip, fabricated in 22-nm fully depleted silicon on insulator (FDSOI) technology, achieves a voltage gain of 13 dB and OOB IIP3/IIP2 of +25+66 dBm with 5-dB noise figure while consuming only 600 μW of power at fLO=1 GHz. Thanks to the transformer, the prototype can operate in the input frequency range of 0.6-1.2 GHz with more than 10-dB voltage gain and 5-9-dB noise figure. Thus, it opens up the possibility of low-power software-defined radios.
In this article, we present a passive mixer-first receiver front end providing a low-power integrated solution for high interference robustness in radios targeting Internet-of-Things (IoT) ...applications. The receiver front end employs a novel N-path filter/mixer, a linear baseband amplifier, and a step-up transformer to realize sub-6-dB NF and >20-dBm OB-IIP3 concurrently. The proposed N-path filter/mixer exploits an implicit capacitive stacking principle to achieve passive voltage gain of 3 during down-conversion and high out-of-band linearity simultaneously while using at least 2<inline-formula> <tex-math notation="LaTeX">\times </tex-math></inline-formula> less total capacitance for the same RF bandwidth compared to a conventional switch-capacitor N-path filter. Fabricated in 22-nm complementary metal-oxide-semiconductor (CMOS) fully depleted silicon on insulator (FDSOI), the receiver prototype-including a 2:6 transformer-occupies only 0.2 mm 2 of active area. Operating in the frequency range of 1.8-2.8 GHz, the front end provides a 45-47-dB conversion gain and a baseband bandwidth of 2 MHz. Due to passive voltage gain in the filter/mixer and transformer, the implemented front end consumes only 1.7-2.5 mW of power to achieve < 6-dB NF, ~24/60/1 dBm out-of-band IIP3/IIP2/B1dB, respectively.
A mixer-first receiver (RX) with enhanced selectivity and high dynamic range is proposed, targeting to remove surface acoustic-wave-filters in mobile phones and cover all frequency bands up to 6 GHz. ...Capacitive negative feedback across the baseband (BB) amplifier serves as a blocker bypassing path, while an extra capacitive positive feedback path offers further blocker rejection. This combination of feedback paths synthesizes a complex pole pair at the input of the BB amplifier, which is upconverted to the RF port to obtain steeper RF bandpass filter roll-off and reduced distortion. This paper explains the circuit principle and analyzes RX performance. A prototype chip fabricated in 45-nm partially depleted silicon on insulator (SOI) technology achieves high out-of-band linearity (input-referred third-order intercept point (IIP3) = 39 dBm and input-referred second-order intercept point (IIP2) = 88 dB) combined with sub-3-dB noise figure. Desensitization due to a 0-dBm blocker is only 2.2 dB at 1.4 GHz.
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