Ultrathin ferroelectric materials could potentially enable low-power perovskite ferroelectric tetragonality logic and nonvolatile memories
. As ferroelectric materials are made thinner, however, the ...ferroelectricity is usually suppressed. Size effects in ferroelectrics have been thoroughly investigated in perovskite oxides-the archetypal ferroelectric system
. Perovskites, however, have so far proved unsuitable for thickness scaling and integration with modern semiconductor processes
. Here we report ferroelectricity in ultrathin doped hafnium oxide (HfO
), a fluorite-structure oxide grown by atomic layer deposition on silicon. We demonstrate the persistence of inversion symmetry breaking and spontaneous, switchable polarization down to a thickness of one nanometre. Our results indicate not only the absence of a ferroelectric critical thickness but also enhanced polar distortions as film thickness is reduced, unlike in perovskite ferroelectrics. This approach to enhancing ferroelectricity in ultrathin layers could provide a route towards polarization-driven memories and ferroelectric-based advanced transistors. This work shifts the search for the fundamental limits of ferroelectricity to simpler transition-metal oxide systems-that is, from perovskite-derived complex oxides to fluorite-structure binary oxides-in which 'reverse' size effects counterintuitively stabilize polar symmetry in the ultrathin regime.
With the exponential increase in the quantity of information to be stored and processed, an important issue that must be urgently resolved for the advancement of modern society is to decrease the ...power consumed by semiconductor devices with high operation speeds. Logic-in-memory (LiM) and neuromorphic devices were proposed as promising solutions to improve the operation speed and energy efficiency by merging logic and memory devices that are classically separated in von Neumann computing systems. Numerous emerging memories were proposed for the LiM and neuromorphic devices of which ferroelectric memories were considered to be one of the most promising candidates since the discovery of unexpected ferroelectricity in complementary metal–oxide–semiconductor compatible binary oxides such as doped HfO
2
. Therefore, a review of binary ferroelectric oxides, from materials to devices, for logic-memory hybrid systems is presented herein.
Graphic abstract
In this work, a L-shaped tunnel FET (TFET), which has the dominant tunneling current in the normal direction to the gate, is introduced with the doping engineering and its electrical characteristics ...are analyzed using TCAD device simulations. The proposed L-shaped TFET has the pocket doping (p + -doping for n-type operations) underlying the gate, which can suppress the corner tunneling generated near the source edge by the electric-field crowding. Thus, the on/off transition is significantly improved since the corner tunneling is the main cause of the degradation of the switching characteristics. To maximize the performance enhancement, the concentration of the pocket doping (<inline-formula> <tex-math notation="LaTeX">{N} _{\mathrm {POC}} </tex-math></inline-formula>) is optimized. As a result, the averaged subthreshold swing (<inline-formula> <tex-math notation="LaTeX">SS_{\mathrm {AVE}} </tex-math></inline-formula>) gets reduced from 60 to 26 mV/dec and the on-current (<inline-formula> <tex-math notation="LaTeX">{I} _{\mathrm {ON}} </tex-math></inline-formula>) becomes ~ 2.0 times increased as compared to the conventional L-shaped TFETs. Moreover, it is confirmed that the pocket doping effectively suppresses the corner tunneling without the on-current reduction even in the extremely scaled gate length (<inline-formula> <tex-math notation="LaTeX">{L} _{\mathrm {G}} </tex-math></inline-formula>) device.
In this study, vertical tunnel FET-based ternary CMOS (T-CMOS) is introduced and its electrical characteristics are investigated using TCAD device and mixed-mode simulations with experimentally ...calibrated tunneling parameters. This new T-CMOS utilizes two different types of tunneling currents to form three different output voltage states: (1) source-to-drain tunneling current; and (2) conventional source-to-channel tunneling current. To form a half supply voltage (<inline-formula> <tex-math notation="LaTeX">\text{V}_{DD} </tex-math></inline-formula>) output voltage during the inverter operation, the n-/p-type devices of the proposed T-CMOS are designed to have constant source-to-drain tunneling current regardless of gate voltage (<inline-formula> <tex-math notation="LaTeX">\text{V}_{GS} </tex-math></inline-formula>) by using nitride spacer between gate and drain. Also, typical binary inverter operation is performed using the source-to-channel tunneling. In voltage transfer characteristics (VTC), it is confirmed that there is the clear half <inline-formula> <tex-math notation="LaTeX">\text{V}_{DD} </tex-math></inline-formula> state after matching the tunneling currents of the n-/p-type devices. It is revealed that the stable half <inline-formula> <tex-math notation="LaTeX">\text{V}_{DD} </tex-math></inline-formula> state cannot be achievable if the currents are mismatched by gate workfunction, gate dielectric thickness, and interface trap variations, implying that the current matching between n-/p-type devices is crucial to obtain stable ternary operations.
Tunnel field-effect transistor (Tunnel FET) with asymmetric spacer is proposed to obtain high on-current and reduced inverter delay simultaneously. In order to analyze the proposed Tunnel FET, ...electrical characteristics are evaluated by technology computer-aided design (TCAD) simulations with calibrated tunneling model parameters. The impact of the spacer κ values on tunneling rate is investigated with the symmetric spacer. As the κ values of the spacer increase, the on-current becomes enhanced since tunneling probabilities are increased by the fringing field through the spacer. However, on the drain-side, that fringing field through the drain-side spacer increases ambipolar current and gate-to-drain capacitance, which degrades leakage property and switching response. Therefore, the drain-side low-κ spacer, which makes the low fringing field, is adapted asymmetrically with the source-side high-κ spacer. This asymmetric spacer results in the reduction of gate-to-drain capacitance and switching delay with the improved on-current induced by the source-side high-κ spacer.
We examine the nature of the interface states induced during the integration of ferroelectric hafnium zirconium oxide on silicon. Metal-ferroelectric-insulator-silicon capacitors, with a thin layer ...of hafnium zirconium oxide grown by atomic layer deposition as the ferroelectric and various interfacial oxide layers as the insulator, are investigated. Since a high-temperature post-annealing is necessary to induce the formation of the ferroelectric phase in this oxide stack, the integrity of the oxide/silicon interface must be preserved after high-temperature processing. As such, we show that a nitrided interlayer provides an improved midgap interface state density among all interfacial oxides investigated. Furthermore, we quantify the interface states using the ac conductance technique and model the interface trap distribution across the silicon bandgap in order to explain and verify the experimental measurements.
With the recently increasing prevalence of deep learning, both academia and industry exhibit substantial interest in neuromorphic computing, which mimics the functional and structural features of the ...human brain. To realize neuromorphic computing, an energy‐efficient and reliable artificial synapse must be developed. In this study, the synaptic ferroelectric field‐effect‐transistor (FeFET) array is fabricated as a component of a neuromorphic convolutional neural network. Beyond the single transistor level, the long‐term potentiation and depression of synaptic weights are achieved at the array level, and a successful program‐inhibiting operation is demonstrated in the synaptic array, achieving a learning accuracy of 79.84% on the Canadian Institute for Advanced Research (CIFAR)‐10 dataset. Furthermore, an efficient self‐curing method is proposed to improve the endurance of the FeFET array by tenfold, utilizing the punch‐through current inherent to the device. Low‐frequency noise spectroscopy is employed to quantitatively evaluate the curing efficiency of the proposed self‐curing method. The results of this study provide a method to fabricate and operate reliable synaptic FeFET arrays, thereby paving the way for further development of ferroelectric‐based neuromorphic computing.
The primary challenge that ferroelectric field‐effect transistors face is their vulnerability to the repeated program/erase cycle. To solve this issue, an efficient self‐curing method is presented. The proposed method successfully recovers synaptic fatigue damage, enhancing learning accuracy in the convolutional neural network.
Reinforcement learning (RL), exhibiting outstanding performance in various fields, requires large amounts of data for high performance. While exploration techniques address this requirement, ...conventional exploration methods have limitations: complexity of hardware implementation and significant hardware burden. Herein, in‐memory RL systems leveraging intrinsic 1/f noise of synaptic ferroelectric field‐effect‐transistors (FeFETs) for efficient exploration are proposed. The electrical characteristics of fabricated FeFETs with low‐power operation capability verify their suitability for neuromorphic systems. The proposed system achieves comparable performance to the conventional exploration method without additional circuits. The intrinsic 1/f noise of the FeFETs facilitates efficient exploration and offers significant advantages: efficiency in hardware implementation and simplicity in adjusting the 1/f noise level for optimal performance. This approach effectively addresses the challenges of conventional exploration methods. The operation mechanism of the exploration method utilizing the 1/f noise is systematically analyzed. The proposed in‐memory RL system demonstrates robustness and reliability to the device‐to‐device variation and the initial conductance distribution. This work provides further insights into the exploration methods of RL, paving the way for advanced in‐memory RL systems.
Exploration techniques play a significant role in reinforcement learning (RL). This study introduces an exploration approach to enhance in‐memory RL using intrinsic 1/f noise of synaptic ferroelectric field‐effect‐transistors. The proposed approach minimizes hardware requirements and offers simplicity in adjusting the noise level to an optimal level. This research paves the way for efficient and flexible hardware‐based RL applications.
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