This paper presents an analog-assisted (AA) output-capacitor-free digital low-dropout (D-LDO) regulator with tri-loop control. For responding to instant load transients, the proposed high-pass AA ...loop momentarily adjusts the unit current of the power switch array, and significantly reduces the voltage spikes. In the proposed D-LDO, the overall 512 output current steps are divided into three sub-sections controlled by coarse/fine loops with carry-in/out operations. Therefore, the required shift register (SR) length is reduced, and a 9-bit output current resolution is realized by using only 28-SR bits. Besides, the coarse-tuning loop helps to reduce the recovery time, while the fine-tuning loop improves the output accuracy. To eliminate the limit cycle oscillation and reduce the quiescent current, a freeze mode is added after the fine-tuning operation. To reduce the output glitches and the recovery time, a nonlinear coarse word control is designed for the carry-in/out operations. The D-LDO is fabricated in a 65-nm general purpose CMOS process. A maximum voltage undershoot/overshoot of 105 mV is measured with a 10-mA/1-ns load step and a total capacitor of only 100 pF. Thus, the resulting figure-of-merit is 0.23 ps.
This article presents an auto-calibration technique for current-based bandgap voltage references (BGRs), based on a digitally-assisted auto-calibration loop for calibration cost reduction. We first ...present a theoretical study of the process variation induced Formula Omitted and Formula Omitted variations in the BJT, which contribute to residual errors in the reference voltage (Formula Omitted) and its temperature coefficient (TC) after applying conventional one-point trimming. Based on the study, we further propose an automatic one-point trimming methodology using a current digital-to-analog converter (IDAC), which can simultaneously relax the Formula OmittedEBand Formula Omitted variations, resulting in a small drift in both Formula Omitted and its TC after calibration. Fabricated in 65 nm standard CMOS, the proposed auto-calibrated BGR achieves a measured TC of 22.3 ppm/°C at 1.2 V supply within −40 °C to 120 °C. The line regulation is 1.26 mV/V or 0.13%/V from 1.2 to 2.5 V. Based on ten-chip measurement results, the achieved Formula Omitted variation in Formula Omitted improves from ±0.53% to ±0.12% within the entire temperature spectrum after applying the proposed auto-calibration technique at 27 °C.
This paper reports a half-rate bang-bang clock and data recovery (BBCDR) circuit supporting the trimodal (NRZ/PAM-4/PAM-8) operation. The observation of their crossover- points distribution at the ...transitions introduces the single-loop phase tracking technique. In addition, low-power techniques at both the architecture and circuit levels are employed to greatly improve the overall energy efficiency and multiply data throughput by increasing the number of levels on the magnitude. Fabricated in 28-nm CMOS, our BBCDR prototype scores a 0.29/0.17/0.14 pJ/bit efficiency at 14.4/28.8/43.2 Gb/s under NRZ/PAM-4/PAM-8 modes, respectively. The jitter is < 0.53 ps (integrated from 100 Hz to 1 GHz) with approximately-equivalent constant loop bandwidth, and we achieve at least 1-UI pp jitter tolerance up to 10 MHz for all the three modes.
This paper presents a fully integrated piezoelectric energy harvesting interface without external components. Instead of relying on bulky external inductors with high quality factor as in the ...conventional parallel-synchronized-switch harvesting-on-inductor (P-SSHI) approach, we propose a flipping-capacitor rectifier (FCR) topology to achieve voltage inversion of the piezoelectric energy harvester through a reconfigurable capacitor array. This fundamentally preserves a fully integrated solution without inductors while achieving a high-energy extraction capability. Measurement results from FCR 1 using discrete components shows an output power enhancement of up to 3.4×, which is close to the theoretical prediction. We also fabricated a sevenphase FCR 3 with four MIM capacitors and 21 switches using a 0.18-μm 1.8/3.3/6 V CMOS process, occupying an active area of ~1.7 mm 2 . Additionally, we implemented an active rectifier based on a common-gate comparator with phase alignment to ensure high-speed operation while minimizing the diode voltage drop. A phase generate-and-combine circuit eliminates redundant switching activities. Systematic optimization of the three main energy loss mechanisms during the finite flip time: 1) phase offset; 2) incomplete charge transfer; and 3) reduced conduction time, is also introduced. Measurement results show that the output power enhancement can reach up to 4.83× at an excitation frequency of 110 kHz.
Titanium dioxide is the most used photocatalyst in wastewater treatment; its semiconductor capacity allows the indirect production of reactive oxidative species. The main drawback of the application ...of TiO2 is related to its high band-gap energy. The nonmetal that is most often used as the doping element is nitrogen, which is due to its capacity to reduce the band-gap energy at low preparation costs. There are multiple and assorted methods of preparation. The main advantages and disadvantages of a wide range of preparation methods were discussed in this paper. Different sources of N were also analyzed, and their individual impact on the characteristics of N–TiO2 was assessed. The core of this paper was focused on the large spectrum of analytical techniques to detect modifications in the TiO2 structure from the incorporation of N. The effect of N–TiO2 co-doping was also analyzed, as well as the main characteristics that are relevant to the performance of the catalyst, such as its particle size, surface area, quantum size effect, crystalline phases, and the hydrophilicity of the catalyst surface. Powder is the most used form of N–TiO2, but the economic benefits and applications involving continuous reactors were also analyzed with supported N–TiO2. Moreover, the degradation of contaminants emerging from water and wastewater using N–TiO2 and co-doped TiO2 was also discussed.
Since the power consumption of data centers keeps increasing, a 48-V rack power distribution system replaces the conventional 12-V power bus to reduce the power delivery IR losses. Meanwhile, the 48 ...V needs conversion into 1 V or lower at the point-of-load for microprocessors. A 48V-to-12V DC-DC converter can serve as a first stage between the huge gap of 48V-to-1V, in a two-stage voltage regulator module (VRM). Thus, this paper presents a 3-phase resonant switched-capacitor (<inline-formula> <tex-math notation="LaTeX">3\Phi </tex-math></inline-formula>-ReSC) converter as the first stage of the VRM. Different from the reported solutions, 3-phase resonant operation reduces the current stress across each small-size GaN switch, and thus improves the power conversion efficiency. In addition, we also present the theoretical analysis and design procedures for the <inline-formula> <tex-math notation="LaTeX">3\Phi </tex-math></inline-formula>-ReSC converter. We demonstrated the proposed <inline-formula> <tex-math notation="LaTeX">3\Phi </tex-math></inline-formula>-ReSC converter with a 98% peak power efficiency at an output current of about 1 A, with a maximum output current of 10 A.
This article presents a radio frequency (RF) rectifier with a wide incident angle of incoming waves, based on a rat-race coupler (RRC). Two identical sub-rectifiers replace the two load circuits of ...the conventional RRC. When compared with the previous Wilkinson power combiner (WPC)-based rectifier, the proposed topology advances with a smaller variation in power conversion efficiency (PCE) over the incident angle. In addition, it simplifies the matching network (MN) design and enables a lower input return loss due to the fully symmetric circuitry between 0° and 180°. Furthermore, it allows a higher design flexibility on the rectifier topology. For validation, we designed and fabricated two wide-angle rectifiers, one working at single band (2.45 GHz) and the other at dual band (0.9 and 2.4 GHz). The single-band rectifier achieved a 67.3% peak PCE and 7.9% efficiency variation within the 0°-360° incident angle range. For the dual-band rectifier, the peak PCE is 78.4% and 70.2%, while the variation is 4% and 8.8%, for 0.9 and 2.4 GHz, respectively. The PCE variation is the smallest among previous works.
The paper focuses on researching the effect of fatigue loading on metallic structure, lifetime, and fracture surface topographies in AISI H13 steel specimens obtained by selective laser melting ...(SLM). The topography of the fracture surfaces was measured over their entire area, according to the entire total area method, with an optical three-dimensional surface measurement system. The fatigue results of the SLM 3D printed steel specimens were compared with those reported for conventionally manufactured 13H steel. The investigation also considers the roughness of the specimens’ side surface. Moreover, the fractographic evaluation conducted using scanning electron microscopy confirms that the predominant fracture mechanism is transgranular fracture. Microtomography done after mechanical loading also showed the influence of the stress level on the porosity distribution. Both fractographic and Micro-CT investigations confirm that higher stresses result in coarser and much more uniform porosity observed in fractured samples. These comprehensive quantitative and qualitative fracture analyses are beneficial to predict the failure conditions of SLM steel parts, especially in the case of fatigue damage. From the quantitative analysis of the H13 SLM-manufactured fracture surface topography, it was possible to conclude that the larger the loadings acting on the specimen, the rougher the fracture surface because the ductile fracture mode dominates. It has also been proven that the porosity degree changes along the length of the sample for the most stressed specimens.
Abstract
Selective laser melting (SLM) is an additive manufacturing powder‐bed fusion process that allows producing complex metallic parts with a relative density of up to 99.9%. Nevertheless, the ...mechanical properties of these components depend on numerous process variables, and there is a lack of systematic studies focused on SLM stainless steels. In the work herein presented, three specific printing strategies were X‐Y patterned to manufacture
Compact Tension
specimens transversally, longitudinally, or chess‐oriented, without any post‐processing heat treatment. The specimens were made of AISI 316L austenitic stainless steel. Thereafter, fatigue crack growth rate (FCGR) tests were carried out at room temperature, at constant amplitude loading (R = 0.2), to determine the fatigue crack propagation constants of the Paris Law associated with each print strategy. It was possible to conclude that transversal additively manufactured specimens showed the lowest FCGRs, and all results were well below the fatigue design curve given in ASME BPVC, Section XI.
Highlights
Three different printing strategies were used to manufacture CT specimens tested.
Fatigue crack growth rates (FCGRs) of additively manufactured AISI 316L SS were determined.
All FCGRs curves obtained were below the fatigue design curve given in ASME BPVC XI.
Mechanisms of crack propagation were determined.
This article reports an ultra-low-power (ULP) Bluetooth low-energy (BLE) receiver with an improved spurious-free dynamic range (SFDR). It features two passive-intensive RF techniques: an ...<inline-formula> <tex-math notation="LaTeX">N </tex-math></inline-formula>-path passive balun-LNA and a pipeline down-mixing baseband (BB)-extraction scheme. They together offer a high-<inline-formula> <tex-math notation="LaTeX">Q </tex-math></inline-formula> bandpass response at RF, and a high passive gain to suppress the noise of the BB hybrid complex filter. Specifically, the balun-LNA is a step-up triple-coil transformer aided by an <inline-formula> <tex-math notation="LaTeX">N </tex-math></inline-formula>-path switched-capacitor (SC) network to perform in-band voltage amplification, high-<inline-formula> <tex-math notation="LaTeX">Q </tex-math></inline-formula> bandpass filtering, <inline-formula> <tex-math notation="LaTeX">I/Q </tex-math></inline-formula> down-mixing, and input-impedance matching. Instead of using active amplifiers as the first-BB gain stage, we passively extract the four-phase (<inline-formula> <tex-math notation="LaTeX">I/Q </tex-math></inline-formula> and differential) BB signals using a pipeline of passive-SC networks that can stack up the voltage gain. Prototyped in TSMC 28-nm CMOS, the BLE receiver consumes only 266 <inline-formula> <tex-math notation="LaTeX">\mu \text{W} </tex-math></inline-formula>, of which 75 <inline-formula> <tex-math notation="LaTeX">\mu \text{W} </tex-math></inline-formula> in the BB hybrid filter at 1 V, and 191 <inline-formula> <tex-math notation="LaTeX">\mu \text{W} </tex-math></inline-formula> in the LO divider + buffer at 0.6 V. Measured at the maximum RF-to-BB gain of 61 dB, the receiver exhibits a noise figure (NF) of 6.1 dB and an out-of-band (OOB)-IIP3 of 22.5 dBm. The corresponding SFDR is 77 dB for a 1-MHz BLE channel and a 10-dB minimum signal-to-noise ratio (SNR<inline-formula> <tex-math notation="LaTeX">_{\mathrm {min}} </tex-math></inline-formula>). The OOB-B−1 dB is −3 dBm.
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