A time latch for high speed time‐based ADCs Abdelaziz, Ahmed; Musah, Tawfiq
Electronics letters,
July 2022, 2022-07-00, 20220701, 2022-07-01, Letnik:
58, Številka:
14
Journal Article
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This letter presents a novel time latch for high speed time domain analogue to digital converters. The time latches reported in literature suffer from a limited maximum operating frequency, which ...makes them unsuitable for high frequency applications. Analysis of the proposed time latch shows it can operate at 10 GHz, 2.5x higher than the best reported time latch. Furthermore, simulations in 28 nm CMOS technology confirm that the enhancement in the speed of the proposed time latch comes with low overhead in area and power. Potential design issues with the proposed time latch are also discussed.
This paper proposes a new authentication approach targeted to wireline broadcast communication systems for automotive and industrial applications. The proposed approach leverages jitter amplification ...in wireline channels, that become stronger features for message-source authentication with higher data rate or channel loss, to provide a low-overhead physical layer authentication. The fundamentals of jitter amplification are reviewed and the use of it as a feature for authentication while maintaining high signal integrity is explored. Simulations using a Simulink model of an example automotive link with multiple electronic control units (ECUs) are used to show the efficacy of the proposed message source authentication scheme. The simulation results also show significant resilience of the proposed approach to noise. Measurement results using a bench-top setup show that the proposed feature detection approach has a high degree of authentication accuracy in a real-time application and provides a low-cost alternative to prevailing software-based approaches.
This paper proposes a hybrid phase detector for use in multilevel timing recovery systems. The proposed approach suppresses errant zero-crossings associated with multilevel baud rate phase detectors ...and ensures maximum signal swing in lock, with minimal hardware and power overhead. Analysis and simulation results in a 28nm CMOS process are used to explore the functionality of proposed phase detector and demonstrate its effectiveness in achieving superior performance to the conventional approach.Clock and data recovery (CDR) loop simulations show that the proposed phase detector enables <inline-formula> <tex-math notation="LaTeX">1.36\times </tex-math></inline-formula> increase in vertical eye margin while maintaining similar steady-state RMS jitter and compared to the conventional approach. The simulations also show effective suppression of unwanted phase detector zero-crossing, while achieving comparable acquisition bandwidth to the conventional approach.
Baud rate timing recovery, for which the Mueller-Muller approach is the most prominent, has become the mainstay of high speed serial links because of the simplicity of its implementation. The ...foundations of Mueller-Muller - Type A timing function and its propensity to lock to erroneous sampling points when applied to high order pulse amplitude modulation is studied. Using the timing error detector characteristics, the probability of the Mueller-Muller - Type A phase detector (PD) to settle to undesirable lock points is investigated. The impact of prevailing approaches to mitigate the effect of this behavior on the performance of clock and data recovery (CDR) systems is quantified, and a new low-overhead PD approach without any of their drawbacks is proposed. Simulink simulations of the CDR phase acquisition, jitter tolerance and timing margins are used to demonstrate the effectiveness of the proposed PD in achieving superior CDR performance while avoiding any of the convergence issues.
This paper proposes receiver complexity reduction by moving the error detection to time domain. The concept of time-based level detection is introduced and its potential to reduce false locking is ...explored. Simulation results are included to show the efficacy of the proposed error extraction approach.
The drive for higher per-lane data rates has led to increased complexity in wireline transceiver architectures due to the need for higher-order equalization. This has the potential to result in ...degraded energy and area efficiency of these transceivers. A new multi-stage decision feedback equalizer (DFE) design approach that leverages speculative intersymbol interference (ISI) cancellation to achieve low complexity is proposed. A 2-tap multi-stage PAM4 DFE design example that uses lower than 35<inline-formula> <tex-math notation="LaTeX">\%</tex-math> </inline-formula> of the components of a conventional speculative DFE, and can be applied to most channel profiles, is used to discuss the equalization capability of the proposed approach. It is also used to discuss the impact of circuit nonidealities on performance. Simulation results of the multi-stage DFE over three different channels showed matched equalization performance to the conventional designs, even as it promises higher data rates than the direct feedback DFE and drastically higher energy efficiency than the conventional speculative DFE.
High-sensitivity optical receivers enable energy-efficient solutions for high-speed optical interconnects. In this article, an analog front-end (AFE), employing a sub-Nyquist CMOS-based ...trans-impedance amplifier (TIA) with post-TIA equalization, is characterized to give an insight on how to design the AFE for optimizing receiver sensitivity and energy-efficiency. Thus, maximizing SNR is targeted. Sub-Nyquist TIA design tradeoffs were analyzed to study the BW limitation impact on linearity and noise. The characterization utilizes idealized NRZ/PAM-4 samplers with DFE/FFE to analyze the equalization complexity. Optimum SNR is reported for different equalizers, specifying the relaxation achieved in TIA BW requirement with respect to the desired data-rate.
This paper does an empirical investigation of the effect of nonlinearity in time-based wireline receivers. The linearity of the voltage-to-time converter (VTC), a necessary component of the ...time-based receiver is simulated, and its impact on the performance of the receiver is studied. Simulation results in a 28nm CMOS process show the effectiveness of using equalization to suppress the effect of VTC nonlinearity and improve the receiver performance.
A wireline receiver complexity reduction approach achieved by using hysteretic extraction of the error for phase detection is presented in this paper. The approach is based on the utilization of the ...data slicers intended for speculative level detection to perform a hysteretic estimation of the error signal. Simulation results showed better jitter tolerance and better eye margin for the proposed hysteretic receiver compared to prior approaches for low loss channels, while reducing the complexity by 64%.
