In this paper, we describe an improved SPICE model for the negative capacitance field-effect transistor (NCFET). According to the law of conservation of charge, the model is built based on the ...relationship between the gate charge of the MOSFET and the charge reserved by the ferroelectric layer and includes the parasitic resistance and capacitance into consideration. Based on the model, the drain-induced barrier lowering (DIBL) and the negative resistance (NR) of the NCFET are analyzed. Finally, taking two well-known analog blocks (the current mirror and the latch comparator) for example, impacts of the DIBL effect and the NR property on analog circuit performances are discussed. Thanks to utilization of the NR feature, not only can impacts of the DIBL effect and the channel-length modulation (CLM) effect be alleviated to improve the mirroring accuracy, but also the comparison speed of the latch comparator be accelerated.
Existing circuit camouflaging techniques to prevent reverse engineering increase circuit-complexity with significant area, energy, and delay penalty. In this paper, we propose an efficient hardware ...encryption technique with minimal complexity and overheads based on ferroelectric field-effect transistor (FeFET) active interconnects. By utilizing the threshold voltage programmability of the FeFETs, run-time reconfigurable inverter-buffer logic, utilizing two FeFETs and an inverter, is enabled. Judicious placement of the proposed logic makes it act as a hardware encryption key and enable encoding and decoding of the functional output without affecting the critical path timing delay. Additionally, a peripheral programming scheme for reconfigurable logic by reusing the existing scan chain logic is proposed, obviating the need for specialized programming logic and circuitry for keybit distribution. Our analysis shows an average encryption probability of 97.43% with an increase of 2.24%/ 3.67% delay for the most critical path/ sum of 100 critical paths delay for ISCAS85 benchmarks.
Negative-capacitance FETs (NCFETs) are a promising candidate for low-power circuits with intrinsic features, e.g., the steep switching slope. Prior works have shown potential for enabling low-power ...digital logic and memory design with NCFETs. Yet, it is still not quite clear how to harness these new features of NCFETs for analog functionalities. This article provides more insights into the circuit design space with new device characteristics and investigates its deployment in analog circuits, specifically, time-domain analog-to-digital converters (ADCs) and phase-locked loops (PLLs). We propose and optimize a novel digital-based clocked comparator and a capacitor-based voltage-to-time converter (VTC), which are essential building blocks in ADCs and PLLs. Evaluation results show beyond-FinFET comparison speed and enhanced linearity for the proposed NCFET-based clocked comparator and VTC, respectively. Such improvement is achieved by exploiting the steeper slope and increased output impedance of NCFETs. More details on design details and a discussion are provided in this article.
Through mixed-mode device and circuit simulation, this paper provides an estimate of the effective output capacitance ( C EFF ) and drive current ( I EFF ) for delay (tau f = 0.69 R sw C EFF , where ...R sw = V DD /2 I EFF ) estimation of unloaded tunnel field-effect transistor (TFET) inverters. It is shown that unlike MOSFET inverters, where C EFF is approximately equal to the gate capacitance ( C gg ) , in TFET inverters, the output capacitance can be as high as 2.6 times the gate capacitance. A three-point model is proposed to extract the effective drive current from the real-time switching current trajectory in a TFET inverter.
Energy harvesting has been widely investigated as a promising method of providing power for ultra-low-power applications. Such energy sources include solar energy, radio-frequency (RF) radiation, ...piezoelectricity, thermal gradients, etc. However, the power supplied by these sources is highly unreliable and dependent upon ambient environment factors. Hence, it is necessary to develop specialized systems that are tolerant to this power variation, and also capable of making forward progress on the computation tasks. The simulation platform in this paper is calibrated using measured results from a fabricated nonvolatile processor and used to explore the design space for a nonvolatile processor with different architectures, different input power sources, and policies for maximizing forward progress.
Non-volatile memories (NVMs) have the potential to reshape next-generation memory systems because of their promising properties of near-zero leakage power consumption, high density and ...non-volatility. However, NVMs also face critical security threats that exploit the non-volatile property. Compared to volatile memory, the capability of retaining data even after power down makes NVM more vulnerable. Existing solutions to address the security issues of NVMs are mainly based on Advanced Encryption Standard (AES), which incurs significant performance and power overhead. In this paper, we propose a lightweight memory encryption/decryption scheme by exploiting in-situ memory operations with negligible overhead. To validate the feasibility of the encryption/decryption scheme, device-level and array-level experiments are performed using ferroelectric field effect transistor (FeFET) as an example NVM without loss of generality. Besides, a comprehensive evaluation is performed on a 128 × 128 FeFET AND-type memory array in terms of area, latency, power and throughput. Compared with the AES-based scheme, our scheme shows ~22.6×/~14.1× increase in encryption/decryption throughput with negligible power penalty. Furthermore, we evaluate the performance of our scheme over the AES-based scheme when deploying different neural network workloads. Our scheme yields significant latency reduction by 90% on average for encryption and decryption processes.
Realizing compact and scalable Ising machines that are compatible with CMOS-process technology is crucial to the effectiveness and practicality of using such hardware platforms for accelerating ...computationally intractable problems. Besides the need for realizing compact Ising spins, the implementation of the coupling network, which describes the spin interaction, is also a potential bottleneck in the scalability of such platforms. Therefore, in this work, we propose an Ising machine platform that exploits the novel behavior of compact bi-stable CMOS-latches (cross-coupled inverters) as classical Ising spins interacting through highly scalable and CMOS-process compatible ferroelectric-HfO
-based Ferroelectric FETs (FeFETs) which act as coupling elements. We experimentally demonstrate the prototype building blocks of this system, and evaluate the scaling behavior of the system using simulations. Our work not only provides a pathway to realizing CMOS-compatible designs but also to overcoming their scaling challenges.
Recently, Memory Augmented Neural Networks (MANN)s, a class of Deep Neural Networks (DNN)s have become prominent owing to their ability to capture the long term dependencies effectively for several ...Natural Language Processing (NLP) tasks. These networks augment conventional DNNs by incorporating memory and attention mechanisms external to the network to capture relevant information. Several MANN architectures have shown particular benefits in NLP tasks by augmenting an underlying Recurrent Neural Network (RNN) with external memory using attention mechanisms. Unlike conventional DNNs whose computational time is dominated by MAC operations, MANNs have more diverse behavior. In addition to MACs, the attention mechanisms of MANNs also consist of operations such as similarity measure, sorting, weighted memory access, and pair-wise arithmetic. Due to this greater diversity in operations, MANNs are not trivially accelerated by the same techniques used by existing DNN accelerators. In this work, we present an end-to-end hardware accelerator architecture,
FARM
, for the inference of RNNs and several variants of MANNs, such as the
Differential Neural Computer
(DNC),
Neural Turing Machine
(NTM) and
Meta-learning model
. FARM achieves an average speedup of 30x-190x and 80x-100x over CPU and GPU implementations, respectively. To address remaining memory bottlenecks in FARM, we then propose the FARM-PIM architecture, which augments FARM with in-memory compute support for MAC and content-similarity operations in order to reduce data traversal costs. FARM-PIM offers an additional speedup of 1.5x compared to FARM. Additionally, we consider an efficiency-oriented version of the PIM implementation, FARM-PIM-LP, that trades a 20% performance reduction relative to FARM for a 4x average power consumption reduction.
This article provides insights into the design of nonvolatile processors (NVPs) for batteryless applications in the Internet of Things (IoT), in which ambient energy-harvesting techniques provide the ...power. Achieving reliable, continuous, forward computation with an unstable, intermittent power supply motivates the transition from conventional volatile processors to emerging NVPs. The authors discuss the various design factors and tradeoffs involved in optimizing this forward progress. This article provides a guide for future IoT applications, revealing inherent features of energy-harvesting NVP design.
