Analog finite-impulse-response (AFIR) filtering is proposed to realize low-power channel selection filters for the Internet-of-Things receivers. High selectivity is achieved using an architecture ...based on only a single-time-varying-transconductance and integration capacitor. The transconductance is implemented as a digital-to-analog converter and is programmable by an on-chip memory. The AFIR operating principle is shown step by step, including its complete transfer function with aliasing. The filter bandwidth and transfer function are highly programmable through the transconductance coefficients and clock frequency. Moreover, the transconductance programmability allows an almost ideal filter response to be realized by careful analysis and compensation of the parasitic circuit impairments. The filter, manufactured in 22-nm FDSOI, has an active area of 0.09 mm 2 . Its bandwidth can be accurately tuned from 0.06 to 3.4 MHz. The filter consumes 92 <inline-formula> <tex-math notation="LaTeX">\mu \text{W} </tex-math></inline-formula> from a 700-mV supply. This low power consumption is combined with a high selectivity: <inline-formula> <tex-math notation="LaTeX">\text{f}_{-60\,\text {dB}}/\text{f}_{-3\,\text {dB}}\,\,= </tex-math></inline-formula> 3.8. The filter has 31.5-dB gain and 12-nV/<inline-formula> <tex-math notation="LaTeX">\sqrt {\text {Hz}} </tex-math></inline-formula> input-referred noise for a 0.43-MHz bandwidth. The OIP3 is 28 dBm, independent of the frequency offset. The output-referred 1-dB-compression point is 3.7 dBm, and the in-band gain compresses by 1 dB for an −3.7-dBm out-of-band input signal while still providing >60 dB of filtering.
Crystal oscillators take a long time and, more importantly, a significant amount of energy to start-up. This article presents a self-timed energy injection technique to quickly start-up a crystal ...oscillator, for very low energy consumption. This is achieved without a power-hungry oscillator to provide the injection signal. The design considerations are discussed, and a prototype crystal oscillator using the proposed technique is integrated into a 22-nm fully depleted silicon-on-insulator (FD-SOI) technology. Connected to a 50-MHz crystal, the manufactured IC achieves a start-up time of 6 μs, for an energy consumption of just 3.7 nJ.
Crystal oscillators can be started up quickly by using energy injection techniques. However, the generation of the injection waveform, as well as driving the large capacitive load formed by the ...crystal, costs a large amount of energy. This article applies the concept of stepwise charging to reduce the energy required to drive the crystal. The energy required to generate the injection waveform by self-timed injection is reduced by using a discrete-time dynamic-bias comparator which uses a simple offset calibration method. Furthermore, the bridge switch resistance is varied dynamically through self-timed control logic to alleviate the accuracy-speed tradeoff. A prototype was manufactured in a 65-nm (triple-well) CMOS technology, which was tested with various crystals ranging from 24 to 50 MHz, improving upon the state of the art in energy consumption.
The Blixer, a Wideband Balun-LNA-I/Q-Mixer Topology Blaakmeer, S.C.; Klumperink, E.; Leenaerts, D.M.W. ...
IEEE journal of solid-state circuits,
12/2008, Letnik:
43, Številka:
12
Journal Article, Conference Proceeding
Recenzirano
Odprti dostop
This paper proposes to merge an I/Q current-commutating mixer with a noise-canceling balun-LNA. To realize a high bandwidth, the real part of the impedance of all RF nodes is kept low, and the ...voltage gain is not created at RF but in baseband where capacitive loading is no problem. Thus a high RF bandwidth is achieved without using inductors for bandwidth extension. By using an I/Q mixer with 25% duty-cycle LO waveform the output IF currents have also 25% duty-cycle, causing 2 times smaller DC-voltage drop after IF filtering. This allows for a 2 times increase in the impedance level of the IF filter, rendering more voltage gain for the same supply headroom. The implemented balun-LNA-I/Q-mixer topology achieves > 18 dB conversion gain, a flat noise figure < 5.5 dB from 500 MHz to 7 GHz, IIP2 = +20 dBm and IIP3 = -3 dBm. The core circuit consumes only 16 mW from a 1.2 V supply voltage and occupies less than 0.01 mm 2 in 65 nm CMOS.
A wide variety of voltage mixers and samplers are implemented with similar circuits employing switches, resistors, and capacitors. Restrictions on duty cycle, bandwidth, or output frequency are ...commonly used to obtain an analytical expression for the response of these circuits. This paper derives unified expressions without these restrictions. To this end, the circuits are decomposed into a polyphase multipath combination of single-ended or differential switched-series-RC kernels. Linear periodically time-variant network theory is used to find the harmonic transfer functions of the kernels and the effect of polyphase multipath combining. From the resulting transfer functions, the conversion gain, output noise, and noise figure can be calculated for arbitrary duty cycle, bandwidth, and output frequency. Applied to a circuit, the equations provide a mathematical basis for a clear distinction between a "mixing" and a "sampling" operating region while also covering the design space "in between." Circuit simulations and a comparison with mixers published in literature are performed to support the analysis.
1.2 Racing Down the Slopes of Moore's Law Nauta, Bram
2024 IEEE International Solid-State Circuits Conference (ISSCC),
2024-Feb.-18, Letnik:
67
Conference Proceeding
Since its inception, Moore's Law has been the driving force for IC design. Although during the first decade, "everything" seemed to be better, however, we lost the scaling of processor clock speed ...and RF transistor speed, and now it looks as if power efficiency of digital gates will stall. What remains is scaling in transistor count and cost-per-function, thanks to 3D integration.Thus, this is an excellent moment to reconsider how we design for analog and digital signal processing. The higher the required signal-to-noise ratio (SNR), the more power-efficient digital signal processing is compared to analog. Pure analog processing remains more efficient only for \sim 30 \mathrm{~dB} SNR or less. In the case of digital processing, the conversion from analog to digital should therefore be made as early in the signal chain as possible. Thanks to the figure-of-merit race, analog-to-digital converters (ADCs) have experienced a tremendous win in power efficiency. However, these ADCs require a large input voltage swing while the input signals to be converted, from an antenna or sensor interface, are usually much smaller. Therefore, RF and analog front-ends are needed, which consume much more power than the ADCs to be driven.Let us re-think these analog front-ends. Can we still efficiently design these front-ends in future CMOS? Do we need so much linear amplification? Do we need active linear circuits at all? Can we not use "digital" components to replace the analog front-ends and ADCs?This paper aims to look at digital and analog processing trends from technology and design fundamentals points of view. We will first zoom out on asymptotic trends in technology scaling and try to identify future design opportunities and challenges. For circuit design, fundamental limits linking power, speed, and accuracy will be reviewed to gain insight into the implications of how we design circuits the way we currently do. This paper aims to create awareness and gives a new vision of designing analog circuits.
This paper presents a set of circuit techniques to achieve high data rate point-to-point communication over long on-chip RC-limited wire-pairs. The ideal line termination impedances for a flat ...transfer function with linear phase (pure delay) are derived, using an s-parameter wire-pair model. It is shown that a driver with series capacitance on the one hand and a resistive load on the other, are fair approximations of these ideal terminations in the frequency range of interest. From a perspective of power efficiency, a capacitive driver is preferred, as the series capacitance reduces the voltage swing along the line which reduces dynamic power consumption. To reduce cross-talk and maintain data integrity, parallel differential interconnects with alternatingly one or two twists are used. In combination with a low offset dynamic sense amplifier at the receiver, and a low-power decision feedback equalization technique with analog feedback, gigabit communication is demonstrated at very low power consumption. A point-to-point link on a 90 nm CMOS test chip achieves 2 Gb/s over 10 mm long interconnects, while consuming 0.28 pJ/bit corresponding to 28 fJ/bit/mm, which is much lower than competing designs.
A discrete-time (DT) mixing architecture for RF-sampling receivers is presented. This architecture makes RF sampling more suitable for software-defined radio (SDR) as it achieves wideband quadrature ...demodulation and wideband harmonic rejection. The paper consists of two parts. In the first part, different downconversion techniques are classified and compared, leading to the definition of a DT mixing concept. The suitability of CT-mixing and RF-sampling receivers to SDR is also discussed. In the second part, we elaborate the DT-mixing architecture, which can be realized by de-multiplexing. Simulation shows a wideband 90° phase shift between I and Q outputs without systematic channel bandwidth limitation. Oversampling and harmonic rejection relaxes RF pre-filtering and reduces noise and interference folding. A proof-of-concept DT-mixing downconverter has been built in 65 nm CMOS, for 0.2 to 0.9 GHz RF band employing 8-times oversampling. It can reject 2nd to 6th harmonics by 40 dB typically and without systematic channel bandwidth limitation. Without an LNA, it achieves a gain of -0.5 to 2.5 dB, a DSB noise figure of 18 to 20 dB, an IIP3 = +10 dBm, and an IIP2 = +53 dBm, while consuming less than 19 mW including multiphase clock generation.
This book describes the design of a high performance time-interleaved ADC, with much attention given to practical design aspects aimed at both industry and research. There is focus on low-power ...design techniques including successive approximation ADCs.
PDF
