A vertical cylindrical SONOS cell with a novel bilayer polysilicon channel down to 22-nm diameter for 3-D NAND Flash memory is successfully developed. We introduce a thin amorphous silicon layer ...along with the oxide-nitride-oxide (ONO) gate stack inside the memory hole. This silicon layer protects the tunnel oxide during opening of the gate stack at the bottom of the memory hole, after which it serves as the first layer of the bilayer polysilicon channel. This approach enables the 3-D architecture to achieve minimum cell area (4 F 2 , with F being the feature size) without the need for the so-called pipeline connections. The smallest functional cells have the memory hole diameter F = 45 nm, resulting in 22-nm channel diameter. In case 16 cells are stacked, F = 45 nm would correspond to an equivalent 11-nm planar cell technology node. Excellent program/erase and retention obtained with the all-deposited ONO stack are demonstrated.
The wind effects on the slopes bounding Giurgeu Depression manifest themselves differently on the forestry landscape according to the features of the abiotic components of environment: geological ...structure, exposition, slope, configuration of secondary valleys, precipitation, drainage, local winds. Forestry landscape of the lower part of the slopes in the depression suffers, almost cyclically, the most visible changes due to wind, even though it is situated in a concave area dominated by calm (60%), but which, by local and occasional amplification of the wind, causes frequent ruptures and breakages of trees (sometimes associated with biotic factors), with negative effects on the activity of population in the area as well as to landscape as a whole. PUBLICATION ABSTRACT
In the Figure (a) the Mo side walls suffer an isotropic etching during the metal gate (MG) patterning (Mo/TiN) due to a poor sidewall passivation when the dry etching was carried out with any Cl2/O2 ...gas mixture. During the MG patterning of MoOx/TiN a more severe isotropic etching of the MoOx was observed using also any ratio of Cl2/O2 gas mixture (b). When the proper amount of HBr gas is added to the Cl2/O2 gas mixture, the side wall passivation of the Mo containing layers is improved suppressing the isotropic etching of Mo or MoOx (c) (the hard-mask has been stripped). Display omitted
► We present the dry etching of Si and Mo(OxNy) based layers on TiN/HfO2 gate stacks. ► Mo based layer are etched isotropically when using any ratio of Cl2/O2 gas mixture. ► The Mo(OxNy) isotropic etching was suppressed by adding HBr to the Cl2/O2 mixture.
Further device scaling below the 65nm node required the introduction of metal gates/high-k layers. This paper discusses the etching approaches for patterning TiN/Mo, TiN/MoOx and TiN/MoOxNy layers used in poly-silicon metal gate stacks. We found that for these Mo based layers, the dry etching using any Cl2/O2 ratio provoked a severe isotropic etching. HBr gas was used as a key component for controlling side-walls passivation. The MoOx and MoOxNy layers were more prone to lateral attack compared to Mo due to the intrinsic stoichiometric oxygen. A good selectivity towards the substrate was obtained using high O2 flows in Cl2/O2/HBr mixtures. Etching of the TiN layer was carried out with Ar/Cl2. This process was tuned by adding HBr depending on the metal gate stack, which suggests that TiN etching is highly influenced by the Mo layer nature (TiN/Mo, TiN/MoOx and TiN/MoOxNy). We have also compared the complete gate stack pattering characteristic when an oxide or an amorphous carbon hard mask has been used for pattern definition.
This work describes the main challenges encountered for patterning crystalline silicon (c-Si) fins when we scaled down the fin pitch from 124 to 90
nm on a 6T-SRAM cell. The target fins consist of ...straight structures (40
nm height and 17
nm of critical dimension) patterned on a 22
nm node with 90
nm fin pitch. The patterning stack consists of 70
nm of amorphous carbon as a hard mask with 25
nm of antireflective coating. Scaling down the fin pitch had a direct influence on the fin critical dimension, profile and sidewall roughness. We found out that the fin etching process developed for a 32
nm node with 124
nm fin pitch was no longer functional for patterning fins on a 22
nm node with 90
nm fin pitch, i.e., the critical dimension was wider than the target, the fins sidewalls were isotropically attacked and the profile was sloped. In order to reach 17
nm of critical dimension on 90
nm pitch we had to implement a new hard mask opening step. The c-Si fin sidewall roughness and fin profile were tuned by improving the uniformity across the wafers, optimizing the softlanding etch time and introducing a new overetch step with notch capability.
Continuous downscaling of integrated circuits brought an end to the era of SiO
2
. In gate dielectrics, it is being replaced by materials with high dielectric constant, so-called high-
k
dielectrics. ...One of the challenges in the integration of the high-
k
material is removal of those materials selectively over the substrate. This work is one of the first attempts to review current state of the art of the high-
k
removal. Two main approaches are discussed: dry (plasma) removal and wet removal. First, the fundamentals and limitations of both approaches are presented, then an overview of the existing experimental data is given. It is concluded that the best results could be obtained by combining the dry and wet approaches.
We demonstrate a self-rectifying, compliance-free, BEOL CMOS-compatible, resistive switching memory device, with nonfilamentary switching mechanism, forming-free operation, analog switching behavior ...and excellent device to device operation uniformity, down to the smallest device size. The cells have a reset switching current density of ~0.3MA/cm 2 (and ~10× lower set current). This corresponds to ~5uA reset current in a 40nm-size cell, projecting down to 1uA for a 20nm-size. The switching currents are tunable by process and structural cell design. The cells can be operated with pulses as short as 10ns, at below ±7V. Cycling for at least 10 6 cy and retention of 55°C/3yr are demonstrated, with clear paths for further improvement. These key features are enabled by the use of an amorphous-Silicon (a-Si) barrier layer, which acts as a semi-insulating oxygen scavenger in a dual-layer a-Si/TiO 2 active stack, being able to provide nonlinear IV cell characteristics, as well as to induce a large oxygen vacancy density in the switching layer.
We report a comprehensive evaluation of different device architectures from a device and circuit performance viewpoint: gate-all-around (GAA) nanowire (NW) FETs vs. triple-gate finFETs, both built ...using various doping schemes. GAA devices are obtained via a fins release process, high density compatible, at replacement metal gate (RMG) module, and outperform others per footprint. Junctionless (JL) GAA-NWFETs with excellent electrostatics and smaller IOFF values yield ring oscillators (RO) with substantially lower power dissipation and considerably longer BTI lifetime. Improved reliability is also obtained for extensionless vs. reference FETs with conventional junctions, at comparable device and circuit performance. In addition, a TiAl-based EWF-metal is introduced for the first time in a GAA configuration resulting in higher performing, low-V T , n-type GAA-NWFETs and single-MG 6T-SRAM cells. Noise results show no significant impact of device architecture on gate stack integrity and some benefit for JL and TiAl-based GAA-NWFETs.
We proposed a new, simpler, and fully BEOL CMOS-compatible TiN/HfO2/TiN RRAM stack using the Plasma Enhanced Atomic Layer Deposition (PEALD) for the top-electrode TiN processing, demonstrating ...attractive bipolar switching properties (by positive RESET voltage to the PEALD TiN) in a functional size down to 2275nm2 (35nm×65nm). Stable switching was observed between a High-Resistive State HRS (∼1MΩ) and a Low-Resistive State LRS (∼100kΩ), using a low program current of ∼1μA. Two different LRS states can be obtained depending on the current compliance (CC) during SET switching, either 100μA (high-CC LRS) or 10μA (low-CC LRS), resulting, respectively in LRS resistances of 10kΩ or 100kΩ. The projected retention stability of low-CC LRS is ⩾10years at 80°C, which is the retention minimum of the TiN/HfO2/TiN RRAM stack. The temperature-dependent resistance showed a non-metallic behavior for the low-CC LRS state (∼100kΩ), suggesting gentle filament formation.
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► CMOS-based patterning of TiN electrodes can reduce the electrochemical characteristics. ► N2/H2-based chemistries are good alternatives to keep the TiN surface intact. ► The use of ...H2O vapor/CF4 can lead to even further improvement.
In this work, we present the impact of standard CMOS-based patterning techniques and more specifically the impact of strip chemistries on the electrochemical behavior of TiN electrodes. As TiN is a material that is both CMOS- and biocompatible, these electrodes are of interest for in vitro and in vivo biomedical applications to interface with electrogenic cells. When scaling down the TiN electrodes to cellular and sub-cellular dimensions, the use of optical lithography in combination with RIE-based (Reactive Ion Etch) patterning will be required. This can be done with standard CMOS processes and tools. However, the TiN etch and more important the subsequent strip of the photoresist are often O2-based. It will be demonstrated that these O2-based chemistries need to be avoided in order to keep the electrode impedance low and its charge injection limit high. The increased surface oxide after exposure to these chemistries decreases the double layer capacitance and reduces the ability of the electrode to transfer charge to the medium and cells. Screening of different strip chemistries, that can be used in the patterning of micrometer sized electrodes, was achieved by electrochemical measurements in combination with XPS analysis on large TiN electrodes. Strip plasmas based on N2/H2 are interesting alternatives to keep the electrode surface intact by reducing the amount of oxygen present at the electrode surface. Moreover, H2O vapor can reduce the surface oxide even further and can lead to lower impedance values and an increased charge storage capacity, beyond the values of the as-deposited layers. The results presented in this paper demonstrate that the scalability of TiN electrodes can be improved significantly when O2-based plasma chemistries are removed from the electrode patterning process. Optimized cleaning after etch and during strip can be beneficial to the overall electrochemical characteristics of the electrode.
