This paper presents a 4.4Gbps/pin all-digital LPDDR4 PHY with a bit-slice architecture in 10nm FinFET process technology. The proposed bit-slice architecture includes new I/O structure for area ...reduction without any off-chip performance degradation and digital duty-tuning capability to maximize the valid window margin, which contributes to low voltage operation in memory interface system. The test chip in 10nm FinFET technology demonstrated stable 4.4Gbps memory access with 112ps valid window margin (49% UI) at 690mV. The implemented 16-bit LPDDR4 PHY occupies only 0.57 mm 2 including a PLL.
This article presents a high-speed all-digital third-generation high-bandwidth memory (HBM3) interface that achieves reliable memory access at a rate of 9.0 Gb/s/pin at 0.66 and 0.30 V supply ...voltages. To enhance the access reliability, the interface uses resistor-tuned offset calibration and in situ margin detection techniques; furthermore, a supply noise adaptation algorithm, coupled with a high-accuracy digital delay sensor, significantly enhances voltage stability and mitigates the degradation of the valid window margin (VWM) under supply voltage variations. Additionally, the use of stacked-I/O and folded-PHY concepts in the HBM3 interface results in an optimal area, enabling seamless alignment with the HBM3 channel structure and effectively minimizing the length of the channels. To demonstrate the effectiveness of the suggested interface, a HBM3 system was implemented with a 4-nm fin field-effect transistor (FinFET) technology. This implementation showcases the outstanding energy efficiency of the HBM3 interface, 0.29 pJ/bit, with an improved supply of noise-tolerance while occupying a small area. This work highlights the promising potential of the proposed all-digital HBM3 interface for enabling high-speed memory access in high-performance computing (HPC)/artificial intelligence (AI) computing systems.
A power reduction scheme that uses ac termination at receiver (RX) and a transmitter (TX) output driver with an active inductor part (AIP) is proposed for a point-to-point post-low-power mobile DRAM4 ...interface at 8 Gb/s. AC termination at the RX I/O can reduce the power consumption by preventing dc power loss. However, this causes inter symbol interference (ISI), owing to the difference in gain depending on the frequency. Thus, ac termination generates more jitter, which results in a smaller eye-opening than the conventional on-die termination. The AIP in the TX output driver reduces the low-frequency gain and the ISI caused by the ac termination. This reduces the jitter and improves the eye-opening. The proposed AIP allows changing the frequency range by adjusting the resistance (<inline-formula> <tex-math notation="LaTeX">{R}_{\mathrm{AI}} </tex-math></inline-formula>), capacitance (<inline-formula> <tex-math notation="LaTeX">{C} _{\mathrm{AI}} </tex-math></inline-formula>), and the size of the MOSFET according to the resistance (<inline-formula> <tex-math notation="LaTeX">{R} _{\mathrm{ac}} </tex-math></inline-formula>) and capacitance (<inline-formula> <tex-math notation="LaTeX">{C} _{\mathrm{ac}} </tex-math></inline-formula>) used in the ac termination at the RX. In this brief, the ac termination at the RX and the AIP in the TX were implemented in a 28-nm CMOS process and operated at 8 Gb/s with a 3-inch FR4 microstrip line including a board and a socket model. The proposed transceiver chip achieves a peak-to-peak jitterof 43.6 ps and power reduction of 31% compared with chips without ac termination and AIP.
As the required data rate has gradually increased in recent years, the phase noise specification of the local oscillator (LO) in the RF standards becomes very stringent. For example, 5G new radio ...(NR) standards demand sub-100fs rms jitter at various channels 1. A conventional charge-pump (CP) PLL is one of the candidates in low noise PLL design. However, to achieve the low in-band noise from the CP, the reset delay of phase-frequency-detector (PFD) should be small, which is difficult to implement since it has trade-off relationship with the dead zone problem of CP and PFD 2 3. A sub-sampling PLL (SSPLL) can achieve a very low in-band noise by sampling the voltage-controlled oscillator (VCO) edge directly and the divider noise can be eliminated 4. However, this architecture has very narrow frequency capture range and its bandwidth suffers from process-voltage-temperature (PVT) variation. A reference sampling PLL (RSPLL) can also significantly reduce in-band noise by sampling behavior similar to SSPLL 1. This structure has moderate capture range and its bandwidth is more insensitive to PVT variation than SSPLL. However both sampling PLLs have a small frequency capture range compared to CPPLLs, they need additional frequency tracking loop (e.g., a frequency-locked loop (FLL)) which leads to increase power and design complexity. In this paper, we propose a low noise RSPLL with a gear shifting (GS) scheme which supports a simple and robust PLL locking process. The proposed PLL is fabricated in a 5nm FinFET CMOS technology and dual frequency bands (16GHz and 10GHz) can be supported. The PLL achieves 33fs rms at 16GHz and 36.6fs rms at 10GHz.
A critical performance bottleneck for memory-bound applications such as high-performance computing (HPC), artificial intelligence (AI), and machine learning (ML) applications is the limited memory ...bandwidth 1. An HBM3 DRAM interface, based on a WDQS-clocking scheme with high-speed low-voltage-swing terminated logic (LVSTL) I/O, is a promising energy-efficient high-bandwidth solution. The WDQS-clocking scheme is expected to improve the read-valid-window margin (VWM), which is a major limiting factor in achieving DRAM access reliability at high speed. However, the long turn-around read path limits the read VWM improvement. In addition, it is essential to minimize interface area for clustered channel implementations by considering controllers, processing units and bus interconnects. Memory-access latency can be minimized by the close placement of functional units to the HBM3 interface.
Recent emerging applications, such as autonomous vehicles, artificial intelligence, and deep learning, require a large amount of data computation. The GDDR6 interface is a candidate solution because ...it can operate up to 64GB/s (16Gb/s/pin x 32 pins) with a lower cost than HBM. To communicate with GDDR6 DRAM 1, 2 the GDDR6 PHY requires high-speed signaling and, more importantly, read/write calibration for optimal margins. In this work, to transmit 18Gb/s data, while meeting the required GDDR6 I/O 1.35V supply, a thin-oxide high-voltage output driver 3 is used with a high-speed level shifter. A dual-mode equalizer is developed in the transmitter to selectively compensate for intersymbol interference (ISI) and far-end crosstalk (FEXT). For an accurate clock-phase calibration and a reduced optimal-reference-voltage search time a simultaneous calibration of clock phase and reference voltage (V REF ) is proposed in receiver. Multiphase gate training is proposed to create an internal source synchronous clock with finite cycles whose 1st rising edge is aligned to the 1st bit of read burst. Then, only valid 16b of a burst data are taken without a post processing.
Although the LPDDR4 interface has enabled industry requirements, such as low power consumption and high bandwidth, additional evolution of the current LPDDR4 performance is expected. To respond to ...the need for more power efficient devices with higher bandwidth, a 2 nd generation LPDDR4 (referred to as LPDDR4X), with extreme low power and extended performance, has been developed in this work. In the controller, the output drivers for data signal (DQ) and data strobe signal (DQS) dominate the power consumption. An efficient method to reduce the output driver power is to reduce the supply voltage (V DDQ ) 1. A low voltage-swing terminated logic (LVSTL) 2 can support this solution by changing the operation region of the pull-up NMOS transistor from the saturation region to the triode region. However, another power supply whose minimum value is V TH_NMOS +V DDQ is required for the pull-up NMOS transistor to serve as source-series termination. In this work, P-over-N topology replaces LVSTL and allows for the use of a single V DDQ (0.6V), thus reducing pre-driver power. Another major improvement in the proposed LPDDR4X controller is that it has functions to compensate for the large variation of DQS output transition time from CK (Δt DQSCK ) 3 due to the lack of a delay locked loop (DLL) in LPDDR4 DRAM 4. Furthermore, the reference voltage on DRAM and the duty cycle of both DQ and DQS are initially calibrated to increase the valid window margin (VWM) during write operations. VWM is the time interval where all DQs remain valid before and after DQS edge in order to capture DQs correctly.
This paper presents practical high-speed and low-power design methodologies for digital PHY in deep sub-micron technologies. The standard-cell-based design approaches with automated place and route ...shorten the design time dramatically. In addition, robust digital design flow can be applied for wide range of operation considering model-hardware-correlation in deep sub-micron technologies. Eventually, all-digital PHY improves power efficiency of the system with wide-voltage-range DVFS. Simplified architecture with calibration logic helps improve logic speed with minimized area and power. The designed PHY with proposed design methodologies shows 1.6Gbps at 520mV and 6.6Gbps at 780mV, which allows extreme power efficiency and performance. In addition, the wide range of voltage scaling is allowed depending on the target frequency.
An all-digital 7.3Gb/s/pin LPDDR5 PHY is presented. A non-interruptive approximate delay compensation scheme is proposed to enhance tolerance to voltage variation without any memory access black-out. ...Thus, seamlessly maintained DQ-centering improves access valid-window-margin under supply noise without performance penalty. In addition to that, the proposed scheme enables direct DVFS switching due to the voltage variation tolerance with minimized performance penalty. The LPDDR5 PHY in an 8nm technology demonstrated 6.4Gb/s/pin with 0.31UI at 640mV and 7.3Gb/s/pin with 0.25UI at 790mV, respectively. The voltage variation tolerance is measured up to 70mV without memory access black-out.
