This paper presents a new radio architecture targeting RF transceivers for WSN, WBAN, and biomedical applications. The high miniaturization required by such applications is achieved thanks to the ...combination of high- Q MEMS devices, such as RF BAW resonators and filters and low frequency silicon resonators, together with a low-power RF IC. This requires a dedicated radio architecture accounting for the advantages and limitations of the MEMS devices. The paper presents such an architecture together with the design of some ultra-low-power and MEMS-specific circuits. The new radio is validated by the demonstration of RX and TX functionalities. The synthesizer, based on a low phase noise BAW DCO and a variable IF LO obtained by fractional division from the RF carrier, achieves a phase noise of - 113 dBc/Hz at 3 MHz. It can intermittently be locked to a low frequency reference (e.g. 32 kHz XTAL or thermally compensated silicon resonator) to correct for the BAW aging and thermal drift thanks to an ADPLL where the lock state can be memorized for nearly immediate settling after returning from an idle period. A sensitivity of - 87 dBm is obtained in receive at 100 kbps for a global power consumption of 6 mA. The transmitter demonstrates a high data rate quasi-direct 1-point modulation capability with the generation of a -4 dBm, 1 Mbps, GFSK signal with an overall current of 20 mA.
In preparation for a silicon pixel detector with more than 3000 readout channels per chip for operation at the future large hadron collider (LHC) at CERN the analog frontend of the readout ...electronics has been designed and measured on several test-arrays with 16 by 4 cells. They are implemented in the HP 0.81 /spl mu/m process but compatible with the design rules of the radiation hard Honeywell 0.8 /spl mu/m bulk process. Each cell contains bump bonding pad, preamplifier, discriminator and control logic for masking and testing within a layout area of only 50 /spl mu/m by 140 /spl mu/m. A new two-level discriminator scheme has been implemented to cope with the problems of time-walk and interpixel cross-coupling. The measured gain of the preamplifier is 900 mV for a minimum ionizing particle (MIP, about 24000 e/sup -/ for a 300 /spl mu/m thick Si-detector) with a return to baseline within 750 ns for a 1MIP input signal. The full readout chain (without detector) shows an equivalent noise charge of 60 e/sup /r.m.s. The time-walk, a function of the separation between the two threshold levels, is measured to be 22 ns at a separation of 1500 e/sup -/, which is adequate for the 40 MHz beam-crossing frequency at the LHC. The interpixel cross-coupling, measured with a 40 fF coupling capacitance, is less than 3%. A single cell consumes 35 /spl mu/W at 3.5 V supply voltage.
Silicon pixel sensors developed by the ATLAS collaboration to meet LHC requirements and to withstand hadronic irradiation to fluences of up to
10
15
n
eq
/
cm
2
have been evaluated using a test beam ...facility at CERN providing a magnetic field. The Lorentz angle was measured and found to alter from 9.0° before irradiation, when the detectors operated at
150
V
bias at
B=1.48
T
, to 3.1° after irradiation and operating at
600
V
bias at
1.01
T
. In addition to the effect due to magnetic field variation, this change is explained by the variation of the electric field inside the detectors arising from the different bias conditions.
The depletion depths of irradiated sensors at various bias voltages were also measured. At
600
V
bias
280
μm
thick sensors depleted to
≈200
μm
after irradiation at the design fluence of
1×10
15
1
MeV
n
eq
/
cm
2
and were almost fully depleted at a fluence of
0.5×10
15
1
MeV
n
eq
/
cm
2
.
The spatial resolution was measured for angles of incidence between 0° and 30°. The optimal value was found to be better than
5.3
μm
before irradiation and
7.4
μm
after irradiation.
A low-power, sparse-scan, readout architecture has been developed for the ATLAS pixel front-end electronics. The architecture supports a dual discriminator and extracts the time over threshold (TOT) ...information along with a 2-D spatial address of the hits and associates them with a unique 7-bit beam crossing number. The IC implements level-1 trigger filtering along with event building (grouping together all hits in a beam crossing) in the end of column (EOC) buffer. The events are transmitted over a 40 MHz serial data link with the protocol supporting buffer overflow handling by appending error flags to events. This mixed-mode full custom IC is implemented in 0.8 /spl mu/ HP process to meet the requirements for the pixel readout in the ATLAS inner detector. The circuits have been tested and the IC has been found to provide dead-time-less ambiguity-free readout at 40 MHz data rate.
The analog front-end of pixel readout electronics with dual threshold discriminator scheme has been measured extensively to determine the optimum performance and performance limitations of the ...circuit. The preamplifier shows a peaking time of 20 ns without capacitive load, which degrades to only 30 ns with a load of 350 fF. The LEVEL-discriminator has an adjustable threshold in the range of 2000 to 6000e/sup -/ with a variable separation to the TIME-discriminator threshold of 800 to 1600e/sup -/. The circuit allows the full suppression of out-of-time signals under the conditions of 350 fF capacitive load and a total power consumption of 40 /spl mu/W per cell. The untuned threshold dispersion is measured to be 320e/sup -/ r.m.s., which reduces to 70e/sup -/ r.m.s. after threshold adjust. The overall noise of the circuit reaches a value of about 200e/sup -/ r.m.s. with 350 fF capacitive load and 20 nA of parallel current at the preamplifier input. Further measurements characterize the time-over-threshold (TOT) behaviour and the double-pulse resolution of the circuit.
A new approach to monolithic pixel detectors, based on silicon on insulator (SOI) wafers with high resistivity substrate, is being pursued by the CERN RD19 collaboration. The fabrication methods and ...the results of the electrical evaluation of the SOI-MOSFET devices and of the detector structures fabricated in the bulk are reported. The leakage current of the high-resistivity PIN-diodes is kept of the order of 5 to 10 nA/cm/sup 2/. The SOI preparation processes employed-SIMOX (separation by implantation of oxygen) and ZMR (zone melting recrystallization)-produce working electronic circuits, and appear to be compatible with the fabrication of detectors of suitable quality.< >
Pixel detector readout cells have been designed in the radiation hard DMILL technology and their characteristics evaluated before and after irradiation to 14 Mrad. The test chip consists of two ...blocks of six readout cells each. Two different charge amplifiers are implemented, one of them using a capacitive feedback loop, the other the fast signal charge transfer to a high impedance integrating node. The measured equivalent noise charge is 110e(-) r.m.s. before and 150e(-) r.m.s. After irradiation. With a discriminator threshold set to 5000e(-), which reduces for the same bias setting to 4000e(-) after irradiation, the threshold variation is 300e(-) r.m.s. and 250e(-) r.m.s. Respectively. The time walk is 40 ns before and after irradiation. The use of this SOI technology for monolithic integration of electronics and detector in one substrate is under investigation.
In this paper, a solution to realize local oscillators (LO) for a low power super-heterodyne receiver is presented. The first oscillator uses a bulk acoustic wave (BAW) resonator with high Q-factor. ...A quasi- harmonic quadrature relaxation oscillator with large tuning range is used to compensate for variations in the first oscillator and to cover the entire bandwidth for multiple channel selection.
Direct parameter extraction on RF-CMOS Pengg, F.X.
2002 IEEE MTT-S International Microwave Symposium Digest (Cat. No.02CH37278),
2002, Letnik:
1
Conference Proceeding, Journal Article
The good knowledge of all parameters of the models used with the circuit simulations is one of the major prerequisites for a successful design. This is particularly true for the design of analog ...radio-frequency (RF) circuits. An efficient and accurate method to directly extract the parameters needed for accurate modeling of transistors in a standard CMOS sub-micron technology for RF-applications is presented. The paper concentrates on the extraction procedure, with emphasis on its simplicity, hence excluding fitting or optimization, and on the accuracy of its results. The extracted parameters are applied to a first order nonquasistatic (NQS) model and the simulation results compared with measurements. Excellent agreement between simulations and measurements up to 50GHz is achieved.
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