The goal of the INFN-RETINA R&D project is to develop and implement a computational methodology that allows to reconstruct events with a large number (> 100) of charged-particle tracks in pixel and ...silicon strip detectors at 40 MHz, thus matching the requirements for processing LHC events at the full bunch-crossing frequency. Our approach relies on a parallel pattern-recognition algorithm, dubbed artificial retina, inspired by the early stages of image processing by the brain. In order to demonstrate that a track-processing system based on this algorithm is feasible, we built a sizable prototype of a tracking processor tuned to 3 000 patterns, based on already existing readout boards equipped with Altera Stratix III FPGAs. The detailed geometry and charged-particle activity of a large tracking detector currently in operation are used to assess its performances. We report on the test results with such a prototype.
We present the first prototype of a silicon tracker using the artificial retina algorithm for fast track finding. The algorithm is inspired by the neurobiological mechanism of recognition of edges in ...mammals visual cortex. It is based on extensive parallelization and is implemented on commercial FPGAs allowing us to reconstruct real time tracks with offline-like quality and <1μs latencies. The practical device consists of a telescope with 8 single-sided silicon strip sensors and custom DAQ boards equipped with Xilinx Kintex 7 FPGAs that perform the readout of the sensors and the track reconstruction in real time.
•First prototype of silicon tracker using the “artificial retina” algorithm.•Algorithm implemented on FPGA to reconstruct tracks with offline quality and sub-μs latencies.•The artificial retina is modular and can be extended to large experiments.•The artificial retina has been proved to be able to work with up to 40MHz.
We present the latest results of an R&D study for a specialized processor capable of reconstructing, in a silicon pixel detector, high-quality tracks from high-energy collision events at 40MHz. The ...processor applies a highly parallel pattern-recognition algorithm inspired to quick detection of edges in mammals visual cortex. After a detailed study of a real-detector application, demonstrating that online reconstruction of offline-quality tracks is feasible at 40MHz with sub-microsecond latency, we are implementing a prototype using common high-bandwidth FPGA devices.
Here, we present the latest results of an R study for a specialized processor capable of reconstructing, in a silicon pixel detector, high-quality tracks from high-energy collision events at 40 MHz. ...The processor applies a highly parallel pattern-recognition algorithm inspired to quick detection of edges in mammals visual cortex. After a detailed study of a real-detector application, demonstrating that online reconstruction of offline-quality tracks is feasible at 40 MHz with sub-microsecond latency, we are implementing a prototype using common high-bandwidth FPGA devices.
We report on the performances of a prototype for a specialized processor capable of reconstructing charged-particle tracks in a realistic Large Hadron Collider (LHC) detector, at full readout speed ...and with sub-microsecond latency. The processor is based on an innovative pattern recognition, called "artificial retina" algorithm, inspired by the vision system of the mammals. A prototype system has been designed, simulated, and implemented on readout boards equipped with Altera Stratix III FPGA devices. This is an important step towards the realization of a real-time track reconstruction device capable of processing complex events of high-luminosity LHC experiments at 40 MHz crossing rate.
We present the first results of the prototype of a silicon tracker with trigger capabilities based on a novel approach for fast track finding. The working principle of the "artificial retina" is ...inspired by the processing of visual images by the brain and it is based on extensive parallelisation of data distribution and pattern recognition. The algorithm has been implemented in commercial FPGAs in three main logic modules: a switch for the routing of the detector hits, a pool of engines for the digital processing of the hits, and a block for the calculation of the track parameters. The architecture is fully pipelined and allows the reconstruction of real-time tracks with a latency less then 100 clock cycles, corresponding to 0.25 microsecond at 400 MHz clock. The silicon telescope consists of 8 layers of single-sided silicon strip detectors with 512 strips each. The detector size is about 10 cm × 10 cm and the strip pitch is 183 μm. The detectors are read out by the Beetle chip, a custom ASICs developed for LHCb, which provides the measurement of the hit position and pulse height of 128 channels. The "artificial retina" algorithm has been implemented on custom data acquisition boards based on FPGAs Xilinx Kintex 7 lx 160. The parameters of the tracks detected are finally transferred to host PC via USB 3.0. The boards manage the read-out ASICs and the sampling of the analog channels. The read-out is performed at 40 MHz on 4 channels for each ASIC that corresponds to a decoding of the telescope information at 1.1 MHz. We report on the first results of the fast tracking device and compare with simulations.
We present the results of a detailed simulation of the artificial retina pattern-recognition algorithm, designed to reconstruct events with hundreds of charged-particle tracks in pixel and silicon ...detectors at LHCb with LHC crossing frequency of \(40\,\rm MHz\). Performances of the artificial retina algorithm are assessed using the official Monte Carlo samples of the LHCb experiment. We found performances for the retina pattern-recognition algorithm comparable with the full LHCb reconstruction algorithm.
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